公开(公告)号：US20240136264A1

公开(公告)日：2024-04-25

申请号：US18374792

申请日：2023-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chiwan SONG ,  Hyunna BAE ,  Joohyung LEE ,  Jaewook JUNG ,  Seungmin BAEK ,  Junghyun CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/08 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/08225 ,  H01L2224/48145 ,  H01L2224/48227

Abstract: A semiconductor package includes: a chip-via composite substrate including a substrate, a semiconductor chip, and a plurality of through vias, wherein the substrate has a first surface and a second surface opposite to the first surface and includes a first region and a second region around the first region, wherein the semiconductor chip is provided in the first region and has chip pads and circuit patterns that are electrically connected to the chip pads, and wherein the plurality of through vias is provided in the second region and penetrate the substrate; a first redistribution wiring layer provided on the first surface of the substrate and having first redistribution wirings that are electrically connected to the chip pads and the through vias; and a second redistribution wiring layer provided on the second surface of the substrate and having second redistribution wirings that are electrically connected to the through vias.

公开(公告)号：US20240234276A9

公开(公告)日：2024-07-11

申请号：US18374792

申请日：2023-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chiwan SONG ,  Hyunna BAE ,  Joohyung LEE ,  Jaewook JUNG ,  Seungmin BAEK ,  Junghyun CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/08 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/08225 ,  H01L2224/48145 ,  H01L2224/48227

Abstract: A semiconductor package includes: a chip-via composite substrate including a substrate, a semiconductor chip, and a plurality of through vias, wherein the substrate has a first surface and a second surface opposite to the first surface and includes a first region and a second region around the first region, wherein the semiconductor chip is provided in the first region and has chip pads and circuit patterns that are electrically connected to the chip pads, and wherein the plurality of through vias is provided in the second region and penetrate the substrate; a first redistribution wiring layer provided on the first surface of the substrate and having first redistribution wirings that are electrically connected to the chip pads and the through vias; and a second redistribution wiring layer provided on the second surface of the substrate and having second redistribution wirings that are electrically connected to the through vias.