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公开(公告)号：US20230005547A1
公开(公告)日：2023-01-05
申请号：US17939012
申请日：2022-09-07
发明人： IN-SU KIM , HYUN JIN CHOI , ALAIN TRAN , BEOM KYU SHIN , WOO SEONG CHEONG
摘要： A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.
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公开(公告)号：US20230152987A1
公开(公告)日：2023-05-18
申请号：US17938291
申请日：2022-10-05
发明人： IN-SU KIM
IPC分类号： G06F3/06
CPC分类号： G06F3/0622 , G06F3/0659 , G06F3/0679
摘要： An operation method of a storage device which includes a nonvolatile memory device and communicates with a host based on a cryptographic key includes setting up a first key identifier and a first lifetime of a first cryptographic key based on a first command received from the host. The method further includes, after the first lifetime is expired, when a second command including the first key identifier is received from the host, performing a data protect operation on the first cryptographic key.
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公开(公告)号：US20220076755A1
公开(公告)日：2022-03-10
申请号：US17191412
申请日：2021-03-03
发明人： IN-SU KIM , HYUN JIN CHOI , ALAIN TRAN , BEOM KYU SHIN , WOO SEONG CHEONG
摘要： A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.
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