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公开(公告)号：US20200287571A1
公开(公告)日：2020-09-10
申请号：US16882627
申请日：2020-05-25
发明人： DONG MIN SHIN , BEOM KYU SHIN , HEON HWA CHEONG , JUN JIN KONG , HONG RAK SON , YEONG GEOL SONG , SE JIN LIM
摘要： A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
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公开(公告)号：US20230005547A1
公开(公告)日：2023-01-05
申请号：US17939012
申请日：2022-09-07
发明人： IN-SU KIM , HYUN JIN CHOI , ALAIN TRAN , BEOM KYU SHIN , WOO SEONG CHEONG
摘要： A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.
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公开(公告)号：US20170359090A1
公开(公告)日：2017-12-14
申请号：US15613659
申请日：2017-06-05
发明人： DONG MIN SHIN , BEOM KYU SHIN , HEON HWA CHEONG , JUN JIN KONG , HONG RAK SON , YEONG GEOL SONG , SE JIN LIM
CPC分类号： H03M13/3927 , G06F11/10 , H03M13/1117
摘要： A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
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公开(公告)号：US20220076755A1
公开(公告)日：2022-03-10
申请号：US17191412
申请日：2021-03-03
发明人： IN-SU KIM , HYUN JIN CHOI , ALAIN TRAN , BEOM KYU SHIN , WOO SEONG CHEONG
摘要： A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.
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公开(公告)号：US20190132010A1
公开(公告)日：2019-05-02
申请号：US16229153
申请日：2018-12-21
发明人： DONG MIN SHIN , BEOM KYU SHIN , HEON HWA CHEONG , JUN JIN KONG , HONG RAK SON , YEONG GEOL SONG , SE JIN LIM
CPC分类号： H03M13/3927 , H03M13/1117
摘要： A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.
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