公开(公告)号：US20160180921A1

公开(公告)日：2016-06-23

申请号：US15056955

申请日：2016-02-29

申请人： Samsung Electronics Co., Ltd.

发明人： In-Chul JEONG

IPC分类号： G11C11/406

CPC分类号： G11C11/40626 ,  G11C7/00 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087

摘要： A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

公开(公告)号：US20140233336A1

公开(公告)日：2014-08-21

申请号：US14059619

申请日：2013-10-22

申请人： Samsung Electronics Co., Ltd.

发明人： Dong-Hak SHIN ,  Yong-Sang PARK ,  Young-Yong BYUN ,  In-Chul JEONG

IPC分类号： G11C7/06

CPC分类号： G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C11/4099

摘要： A semiconductor device may comprise a first bit line, a second bit line, a memory cell connected to the first bit line, a bit line sense amplifier circuit and a control circuit. The bit line sense amplifier circuit may be coupled to the memory cell. The bit line sense amplifier circuit may include a first inverter having an input node coupled to the first bit line and an output node coupled to the second bit line, and a second inverter having an input node coupled to the second bit line and an output node coupled to the first bit line. The control circuit may be configured to activate the first inverter without activating the second inverter during a first time period and to activate the first inverter and the second inverter at the same time during a second time period after the first time period.

摘要翻译： 半导体器件可以包括第一位线，第二位线，连接到第一位线的存储器单元，位线读出放大器电路和控制电路。 位线读出放大器电路可以耦合到存储单元。 位线读出放大器电路可以包括具有耦合到第一位线的输入节点和耦合到第二位线的输出节点的第一反相器，以及耦合到第二位线的输入节点和输出节点 耦合到第一位线。 控制电路可以被配置为在第一时间段内激活第一逆变器而不启动第二逆变器，并且在第一时间段之后的第二时间段期间同时激活第一逆变器和第二逆变器。

公开(公告)号：US20150221362A1

公开(公告)日：2015-08-06

申请号：US14685912

申请日：2015-04-14

申请人： Samsung Electronics Co., Ltd.

发明人： In-Chul JEONG

IPC分类号： G11C11/406 ,  G11C11/408

CPC分类号： G11C11/40626 ,  G11C7/00 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4087

摘要： A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

摘要翻译： 半导体存储器件包括存储单元阵列，刷新控制电路，地址计数器和地址转换器。 存储单元阵列包括多个存储单元。 刷新控制电路被配置为在一个刷新周期期间接收刷新命令并输出m个刷新控制信号，以刷新半导体存储器件的所有存储单元。 地址计数器被配置为响应于m个刷新控制信号产生用于刷新存储器单元的计数信号。 地址转换器被配置为通过响应于周期选择信号转换计数信号来接收计数信号并输出​​刷新地址。 地址转换器被配置为输出刷新地址，使得在一个刷新周期期间的m个刷新控制信号的数量是可变的。

公开(公告)号：US20140269134A1

公开(公告)日：2014-09-18

申请号：US14197437

申请日：2014-03-05

申请人： Samsung Electronics Co., Ltd.

发明人： Young-Hun KIM ,  In-Chul JEONG

IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/401

CPC分类号： G11C11/408 ,  G11C7/1063 ,  G11C11/40611

摘要： A method of controlling a refresh operation for a memory device is disclosed. The method includes storing a first row address corresponding to a first row of a memory cell array, storing one or more second row addresses corresponding to one or more second rows of the memory cell array, the one or more second row addresses corresponding to the first row address, sequentially generating row addresses as a refresh row address during a first refresh interval, for each generated row address, when a generated row address identical to one of the one or more second row addresses is detected, stopping the generation of row addresses and sequentially outputting the one second row address and the first row address as the refresh row address, restarting the generation of the row addresses as the refresh row address after outputting the one second row address and the first row address.

摘要翻译： 公开了一种控制存储器件刷新操作的方法。 该方法包括存储对应于存储单元阵列的第一行的第一行地址，存储对应于存储单元阵列的一个或多个第二行的一个或多个第二行地址，对应于第一行地址的第一行地址 行地址，当检测到与所述一个或多个第二行地址中的一个相同的生成行地址时，针对每个生成的行地址，在第一刷新间隔期间顺序地生成行地址作为刷新行地址，停止生成行地址， 顺序地输出一个第二行地址和第一行地址作为刷新行地址，在输出一个第二行地址和第一行地址之后重新开始生成行地址作为刷新行地址。

公开(公告)号：US20140198593A1

公开(公告)日：2014-07-17

申请号：US14158067

申请日：2014-01-17

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sang-Hyuk KWON ,  In-Chul JEONG

IPC分类号： G11C29/04

CPC分类号： G11C29/04 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/4402

摘要： A redundancy circuit includes a redundancy decoder, a fuse array, and a decoder. The redundancy decoder decodes a redundancy enable signal generated when an address of a defective cell matches an input address. The decoded redundancy enable signal is used to activate a spare column select line connected with a redundancy block to be substituted for the defective cell designated by the defective cell address. The fuse array includes fuse elements to designate segments in the redundancy block based on availability of the segments. The decoder decodes coding signals from the fuse array to connect at least one of the fuse elements with the spare column select line.

摘要翻译： 冗余电路包括冗余解码器，熔丝阵列和解码器。 冗余解码器解码当缺陷单元的地址与输入地址匹配时产生的冗余使能信号。 解码冗余使能信号用于激活与冗余块连接的备用列选择线，以替代由缺陷单元地址指定的缺陷单元。 保险丝阵列包括根据段的可用性来指定冗余块中的段的熔丝元件。 解码器解码来自熔丝阵列的编码信号，以将至少一个熔丝元件与备用列选择线连接。