公开(公告)号：US20200273877A1

公开(公告)日：2020-08-27

申请号：US16550591

申请日：2019-08-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JANG-GN YUN ,  JAE-DUK LEE

IPC: H01L27/11582 ,  G11C16/04 ,  G11C16/14 ,  H01L23/528 ,  H01L27/11573

Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

公开(公告)号：US20170062468A1

公开(公告)日：2017-03-02

申请号：US15189205

申请日：2016-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HWAN SON ,  YOUNG-WOO PARK ,  JAE-DUK LEE

IPC: H01L27/115 ,  G11C16/26 ,  H01L23/535

CPC classification number: H01L27/11582 ,  H01L27/1157

Abstract: A non-volatile memory device having a vertical structure includes: a first interlayer insulating layer on a substrate; a first gate electrode disposed on the first interlayer insulating layer; second interlayer insulating layers and second gate electrodes alternately stacked on the first gate electrode; an opening portion penetrating the first gate electrode, the second interlayer insulating layers, and the second gate electrodes and exposing the first interlayer insulating layer; a gate dielectric layer covering side walls and a bottom surface of the opening portion; and a channel region formed on the gate dielectric layer, and penetrating a bottom surface of the gate dielectric layer and the first interlayer insulating layer and thus electrically connected to the substrate, wherein a separation distance between side walls of the gate dielectric layer in a region which contacts the first gate electrode is greater than that in a region which contacts any one of the second gate electrodes.

Abstract translation: 具有垂直结构的非易失性存储器件包括：衬底上的第一层间绝缘层; 设置在所述第一层间绝缘层上的第一栅电极; 第二层间绝缘层和交替层叠在第一栅电极上的第二栅电极; 穿过所述第一栅电极，所述第二层间绝缘层和所述第二栅电极的开口部分，并暴露所述第一层间绝缘层; 覆盖所述开口部的侧壁和底面的栅介质层; 以及沟道区，形成在所述栅极电介质层上，并且穿透所述栅极电介质层和所述第一层间绝缘层的底表面，从而电连接到所述衬底，其中所述栅极电介质层的侧壁之间的间隔距离在区域 与第一栅电极接触的区域大于与第二栅电极接触的区域。

公开(公告)号：US20210319832A1

公开(公告)日：2021-10-14

申请号：US17357494

申请日：2021-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JANG-GN YUN ,  JAE-DUK LEE

IPC: G11C16/14 ,  G11C16/04

Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.

公开(公告)号：US20210082518A1

公开(公告)日：2021-03-18

申请号：US17092896

申请日：2020-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JANG-GN YUN ,  JAE-DUK LEE

IPC: G11C16/14 ,  G11C16/04

Abstract: An integrated circuit device includes channel structures extending from a substrate in a vertical direction, memory cell strings disposed along the plurality of channel structures, gate lines spaced apart from one another in the vertical direction and including erase control lines and string selection lines, and driving transistors including erase control driving transistors connected to the erase control lines and string selection driving transistors connected to the string selection lines.