公开(公告)号：US20200350330A1

公开(公告)日：2020-11-05

申请号：US16700059

申请日：2019-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGSEON AHN ,  JAERYONG SIM ,  GIYONG CHUNG ,  JEEHOON HAN

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/06 ,  H01L21/311 ,  H01L23/60

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor lavers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

公开(公告)号：US20230247835A1

公开(公告)日：2023-08-03

申请号：US18055200

申请日：2022-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAERYONG SIM ,  DONGHYUCK JANG ,  JEEHOON HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11565 ,  H01L27/11573

Abstract: Disclosed are 3D semiconductor memory device, electronic systems including the same, and methods of fabricating the same. The 3D semiconductor memory device includes lower selection lines extending in a first direction on a substrate and spaced apart from each other in a second direction that is parallel to a top surface of the substrate and intersects the first direction, a middle stack structure including electrode layers and electrode interlayer dielectric layers that are alternately stacked on the lower selection lines, upper selection lines extending in the first direction on the middle stack structure and spaced apart from each other in the second direction, a first polishing stop layer disposed between the middle stack structure and the lower selection lines. The first polishing stop layer includes a material different from that of the electrode interlayer dielectric layers.

公开(公告)号：US20220149060A1

公开(公告)日：2022-05-12

申请号：US17362903

申请日：2021-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAERYONG SIM ,  Giyong Chung ,  Dongsik Oh ,  Jeehoon Han

IPC: H01L27/11529 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/423 ,  H01L21/28

Abstract: A semiconductor device includes a substrate that includes a first active region, a second active region, and an isolation region. An isolation layer pattern fills a trench in the substrate. A first gate insulation layer pattern and a first gate, electrode structure are formed on the first active region. A second gate insulation layer pattern and second gate electrode structure are formed on the second active region. The first gate electrode structure includes a first polysilicon pattern, a second polysilicon pattern, and a first metal pattern. The second gate electrode structure includes a third polysilicon pattern, a fourth polysilicon pattern, and a second metal pattern. An upper surface of the isolation layer pattern is higher than upper surfaces of each of the first and third polysilicon patterns. A sidewall of each of the first and third polysilicon patterns contacts sidewalls of the isolation layer pattern.

公开(公告)号：US20210036010A1

公开(公告)日：2021-02-04

申请号：US16842252

申请日：2020-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAERYONG SIM ,  JONGSEON AHN ,  JEEHOON HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522

Abstract: A semiconductor memory device includes horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other in a first direction. Memory structures are disposed on the horizontal patterns. The memory structures include source structures and electrode structures. A division structure is disposed between adjacent horizontal patterns in the first direction and is configured to separate the source structures of adjacent memory structures from each other. An etch stop pattern is disposed between the horizontal patterns at a level lower than a level of the source structures. The etch stop pattern is connected to a lower portion of the division structure.