公开(公告)号：US20250046728A1

公开(公告)日：2025-02-06

申请号：US18429538

申请日：2024-02-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongwon KANG ,  Hongwon KIM ,  Changyeon SONG ,  Sunguk LEE ,  Jae-Ean LEE

IPC: H01L23/544 ,  H01L23/00 ,  H01L23/498

Abstract: A semiconductor package may include a semiconductor chip and an upper redistribution layer including a marking structure on the semiconductor chip, an upper insulating layer surrounding the marking structure, and an outer insulating layer on the upper insulating layer, wherein the marking structure may include a lower marking pattern, a marking via on the lower marking pattern, and an upper marking pattern on the marking via, the upper marking pattern may include a first conductive pattern on the marking via and a second conductive pattern on the first conductive pattern, and the second conductive pattern may be exposed by a trench defined by the outer insulating layer.

公开(公告)号：US20230134541A1

公开(公告)日：2023-05-04

申请号：US17836711

申请日：2022-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Ean LEE ,  Gyu Jin CHOI

IPC: H01L23/498 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor package is provided. The semiconductor package includes: a substrate; a first semiconductor chip provided on an upper surface of the substrate; an interposer provided on the first semiconductor chip; a conductive pad provided on the upper surface of the substrate; and a connecting portion provided between the upper surface of the substrate and a lower surface of the interposer, wherein the connecting portion is spaced apart from the first semiconductor chip along a horizontal direction parallel to the upper surface of the substrate, and electrically connects the conductive pad and the interposer, and the connecting portion includes a first metal layer provided on the conductive pad, a second metal layer provided on the first metal layer, and a metal post provided on the second metal layer, wherein the first metal layer includes a first metal, the second metal layer includes a second metal different from the first metal, and the metal post includes a third metal different from the first metal and the second metal.

公开(公告)号：US20240071895A1

公开(公告)日：2024-02-29

申请号：US18353279

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seoeun KYUNG ,  Byung Ho KIM ,  Youngbae KIM ,  Hongwon KIM ,  Seokwon LEE ,  Jae-Ean LEE ,  Dahee KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L25/10 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/105 ,  H01L25/18 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5385 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor package may include a lower redistribution layer including a lower wiring and a lower via, an embedded region on the lower redistribution layer, a core layer on the lower redistribution layer and including a core via, and an under bump structure including an under bump pad on a lower surface of the lower redistribution layer and an under bump via connecting the lower wiring and the under bump pad, the under bump pad may overlap the under bump via, the lower via, and the core via in a plan view, and the under bump via may be spaced apart from at least one of the lower via and the core via in the plan view.