公开(公告)号：US20240379515A1

公开(公告)日：2024-11-14

申请号：US18419694

申请日：2024-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyoungok Jung ,  Jakyoung Gu ,  Seonghyun Yoo

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package, that includes: a first semiconductor chip including first pads; a second semiconductor chip including second pads on a first surface facing the first semiconductor chip and in contact with the first pads, and including through-electrodes electrically connected to the second pads and extending to a second surface, opposite to the first surface; a first dielectric layer that covers the rear surface of the second semiconductor chip and a portion of each of side surfaces of the through-electrodes thereof; a second dielectric layer that surrounds a side surface of the second semiconductor chip; and bump structures on a planar surface defined by the first dielectric layer and the second dielectric layer, and electrically connected to the through-electrodes, The first dielectric layer may include an inorganic compound, and the second dielectric layer may include an organic-inorganic composite material having a lower coefficient of thermal expansion than the inorganic compound.

公开(公告)号：US20250069899A1

公开(公告)日：2025-02-27

申请号：US18751384

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jakyoung Gu ,  Kyoungok Jung ,  Jihye Shim

IPC: H01L21/48 ,  G03F7/00 ,  G03F7/20 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: In a method of manufacturing a semiconductor package, a lower redistribution wiring layer having a central region and a peripheral region surrounding the central region is formed. A photosensitive insulating layer is formed on the lower redistribution wiring layer. A first light is radiated onto the photosensitive insulating layer through a first mask to form a first hardened portion on the central region. A second light is radiated onto the photosensitive insulating layer through a second mask to form a second hardened portion on the peripheral region, the second hardened portion surrounding through opening regions. Non-hardened portions in the through opening regions and at least a portion of the first hardened portion are removed. Conductive structures are formed in the through opening regions. The second hardened portion and the remainder of the first hardened portion are removed using a strip solution.

公开(公告)号：US20250070002A1

公开(公告)日：2025-02-27

申请号：US18667800

申请日：2024-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungtae Kim ,  Minsoo Kim ,  Jakyoung Gu ,  Kyoungok Jung ,  Hyunwoong Han

IPC: H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor package, may include: a lower redistribution structure including lower redistribution layers; a semiconductor chip on the lower redistribution structure, and electrically connected to the lower redistribution layers; connection bumps on the lower redistribution structure, and electrically connected to the lower redistribution layers; an encapsulant covering at least a portion of the semiconductor chip; an upper redistribution structure including an upper insulating layer on the semiconductor chip, and upper redistribution layers including a metal structure on the upper insulating layer; an interconnection structure that electrically connects the lower redistribution layers and the upper redistribution layer; and a metal plate on an upper surface of the metal structure, wherein the upper surface may have a first surface, a second surface around the first surface, and a third surface around the second surface, the first surface may be on the same or higher level than that of the second surface.