公开(公告)号：US20240136201A1

公开(公告)日：2024-04-25

申请号：US18381905

申请日：2023-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO ,  Junhyeong Park ,  Jieun Park ,  Jihye Shim ,  Jiyoung Lee

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L24/04

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.

公开(公告)号：US20230411267A1

公开(公告)日：2023-12-21

申请号：US18128069

申请日：2023-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyeong Kim ,  Jinyoung Kim ,  Jihye Shim ,  Okseon Yoon

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L23/49894 ,  H01L25/105 ,  H01L23/49816 ,  H01L24/08 ,  H01L24/16 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2224/08235 ,  H01L2224/16235 ,  H01L2924/182

Abstract: A semiconductor package includes a redistribution structure including a wiring structure and an insulating structure covering the wiring structure, the redistribution structure having a first surface and a second surface, which are opposite to each other, the insulating structure including a polymer, a semiconductor chip on the first surface, the semiconductor chip being connected to at least one first wiring pattern in the wiring structure, a passivation insulating film covering the second surface, the passivation insulating film including an inner surface contacting the insulating structure and a hole sidewall defining a hole, the passivation insulating film including an inorganic insulating material, a conductive pad passing through the passivation insulating film via the hole and contacting the second wiring pattern, the conductive pad having a pad sidewall contacting the hole sidewall, and an external connection terminal on the conductive pad.

公开(公告)号：US20250132202A1

公开(公告)日：2025-04-24

申请号：US18816416

申请日：2024-08-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seokkyu Lee ,  Wonbin Shin ,  Kiseok Kim ,  Jihye Shim ,  Jeonggi Jin

IPC: H01L21/768

Abstract: A method of manufacturing a semiconductor package with a semiconductor chip including an active surface and an inactive surface opposite to the active surface is presented. The method includes attaching, to the active surface, a film structure including an insulating layer and a first seed layer contacting the insulating layer. A via hole is formed by penetrating the insulating layer and the first seed layer followed by a descumming the insulating layer and the first seed layer in which the via hole is formed. A second seed layer is formed on the insulating layer and on the first seed layer on which the descum process was performed. A photoresist pattern on the second seed layer enables forming a conductive via by filling both a space defined by the via hole with a conductive material and by filling a space defined by the photoresist pattern with the conductive material.

公开(公告)号：US20240234165A9

公开(公告)日：2024-07-11

申请号：US18381905

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuseon HEO ,  Junhyeong Park ,  Jieun Park ,  Jihye Shim ,  Jiyoung Lee

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L21/4857 ,  H01L23/3128 ,  H01L23/49838 ,  H01L25/18 ,  H10B80/00 ,  H01L24/04

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, coating a high transmittance photoresist on the first wiring structure a plurality of number of times, forming a plurality of openings by exposing and developing the high transmittance photoresist, forming a plurality of conductive posts by filling the plurality of openings with a conductive material, removing the high transmittance photoresist, disposing a semiconductor chip on the first wiring structure, forming an encapsulant surrounding the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the light transmittance of the high transmittance photoresist at a portion where the first wiring structure and the high transmittance photoresist contact each other is greater than or equal to 3.2%.

公开(公告)号：US20240194582A1

公开(公告)日：2024-06-13

申请号：US18523970

申请日：2023-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokkyu Lee ,  Jihye Shim ,  Kiseok Kim ,  Wonbin Shin

IPC: H01L23/498 ,  H01L23/31

CPC classification number: H01L23/49894 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/08 ,  H01L2224/08235

Abstract: A semiconductor package includes a redistribution substrate having a first surface and a second surface opposite to each other, and including a plurality of first photosensitive insulating layers and a plurality of redistribution layers disposed among the plurality of first photosensitive insulating layers; at least one semiconductor chip disposed on the first surface of the redistribution substrate and including a plurality of contact pads electrically connected to the plurality of redistribution layers; a protective insulating layer including a second photosensitive insulating layer disposed on the second surface of the redistribution substrate and having a plurality of contact holes, and a non-photosensitive insulating layer disposed on an outer surface of the second photosensitive insulating layer and an internal sidewall of each of the plurality of contact holes; and a plurality of under bump metallurgy (UBM) connectors each having a UBM pad disposed on the protective insulating layer and a UBM via disposed in a respective contact hole of the plurality of contact holes and electrically connected to the plurality of redistribution layers.

公开(公告)号：US20240136332A1

公开(公告)日：2024-04-25

申请号：US18483545

申请日：2023-10-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Yuseon Heo ,  Jihye Shim ,  Junhyeong Park

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/48106 ,  H01L2224/73215 ,  H01L2225/06527

Abstract: Provided is a method of manufacturing a semiconductor package, the method including forming a first wiring structure, forming a multi-layer photoresist on the first wiring structure, forming a plurality of openings in the multi-layer photoresist by exposing and developing the multi-layer photoresist, forming a plurality of conductive posts by forming a conductive material in the plurality of openings, removing the multi-layer photoresist, providing a semiconductor chip on the first wiring structure, forming an encapsulant on the semiconductor chip and the plurality of conductive posts, and forming a second wiring structure on the encapsulant, wherein the multi-layer photoresist includes at least two layers having different light transmittances.

公开(公告)号：US20250167153A1

公开(公告)日：2025-05-22

申请号：US18932984

申请日：2024-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Okseon Yoon ,  Jinyoung Kim ,  Jiyoung Yoon ,  Kiseok Kim ,  Jihye Shim

IPC: H01L23/00 ,  G03F7/028

Abstract: A method of forming a redistribution pad, the method including forming a hole exposing a redistribution pattern in a redistribution insulating layer and forming a photoresist composition on a surface of the redistribution insulating layer and filling the hole. The photoresist composition including at least one first photoinitiator and at least one first crosslinking agent that cause a crosslinking reaction by a first light and at least one second photoinitiator and at least one second crosslinking agent that cause a crosslinking reaction by a second light having a different wavelength from the first light. The method further includes irradiating the first light to the photoresist composition, forming a photoresist pattern having a pattern hole using the photoresist composition to which the first light is irradiated, irradiating the second light to the photoresist pattern, and forming the redistribution pad using the photoresist pattern to which the second light is irradiated.

公开(公告)号：US20250140727A1

公开(公告)日：2025-05-01

申请号：US18891191

申请日：2024-09-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonbin Shin ,  Jihye Shim ,  Seokkyu Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/49

Abstract: Provided is a wiring structure including a wiring insulating layer including a first insulating layer and a second insulating layer on the first insulating layer, and a wiring pattern that penetrates the second insulating layer and extends into the first insulating layer, wherein a portion of a side surface of the wiring pattern in contact with the first insulating layer is a curved surface with a first surface roughness, and a portion of the side surface of the wiring pattern in contact with the second insulating layer is a flat surface with a second surface roughness that is less than the first surface roughness.

公开(公告)号：US20250125205A1

公开(公告)日：2025-04-17

申请号：US18674416

申请日：2024-05-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Park ,  Kiseok Kim ,  Jinyoung Kim ,  Jihye Shim

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including first pads, a second semiconductor chip including second pads in contact with the first pads, and through-electrodes electrically connected to the second pads and extending to a rear surface opposite to the front surface, a dielectric layer covering at least portions of the respective first and second semiconductor chips and having an inner surface facing the first and second semiconductor chips and an outer surface opposite the inner surface, and bump structures on a portion of the outer surface of the dielectric layer and electrically connected to the through-electrodes. The dielectric layer includes inorganic particles, and polymer chains bonded to at least one sides of the respective inorganic particles and connected toward the inner surface and the outer surface via the inorganic particles.

公开(公告)号：US20250069899A1

公开(公告)日：2025-02-27

申请号：US18751384

申请日：2024-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jakyoung Gu ,  Kyoungok Jung ,  Jihye Shim

IPC: H01L21/48 ,  G03F7/00 ,  G03F7/20 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: In a method of manufacturing a semiconductor package, a lower redistribution wiring layer having a central region and a peripheral region surrounding the central region is formed. A photosensitive insulating layer is formed on the lower redistribution wiring layer. A first light is radiated onto the photosensitive insulating layer through a first mask to form a first hardened portion on the central region. A second light is radiated onto the photosensitive insulating layer through a second mask to form a second hardened portion on the peripheral region, the second hardened portion surrounding through opening regions. Non-hardened portions in the through opening regions and at least a portion of the first hardened portion are removed. Conductive structures are formed in the through opening regions. The second hardened portion and the remainder of the first hardened portion are removed using a strip solution.