公开(公告)号：US20230013064A1

公开(公告)日：2023-01-19

申请号：US17947397

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop LEE ,  Hwanwook PARK ,  Jeonghoon BAEK ,  Dohyung KIM ,  Seunghee MUN ,  Dongyoon SEO ,  Jinoh AHN

IPC: H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40 ,  G11C5/04

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.

公开(公告)号：US20220159827A1

公开(公告)日：2022-05-19

申请号：US17337850

申请日：2021-06-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop LEE ,  Hwanwook PARK ,  Jeonghoon BAEK ,  Dohyung KIM ,  Seunghee MUN ,  Dongyoon SEO ,  Jinoh AHN

IPC: H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.