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公开(公告)号：US20210375823A1
公开(公告)日：2021-12-02
申请号：US17142133
申请日：2021-01-05
发明人： Jihwan HWANG , Unbyoung KANG , Sangsick PARK , Jihwan SUH , Soyoun LEE , Teakhoon LEE
IPC分类号： H01L23/00 , H01L23/498 , H01L25/065
摘要： A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.
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公开(公告)号：US20220344308A1
公开(公告)日：2022-10-27
申请号：US17861580
申请日：2022-07-11
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
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公开(公告)号：US20220285312A1
公开(公告)日：2022-09-08
申请号：US17804110
申请日：2022-05-26
发明人： Jihwan HWANG , Unbyoung KANG , Sangsick PARK , Jihwan SUH , Soyoun LEE , Teakhoon LEE
IPC分类号： H01L23/00 , H01L25/065 , H01L23/498
摘要： A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.
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公开(公告)号：US20220130801A1
公开(公告)日：2022-04-28
申请号：US17568558
申请日：2022-01-04
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/538 , H01L23/31 , H01L23/16
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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公开(公告)号：US20210151410A1
公开(公告)日：2021-05-20
申请号：US17036508
申请日：2020-09-29
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
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公开(公告)号：US20210028152A1
公开(公告)日：2021-01-28
申请号：US16833761
申请日：2020-03-30
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/16 , H01L23/31 , H01L23/538
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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