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公开(公告)号：US20230225117A1
公开(公告)日：2023-07-13
申请号：US17862638
申请日：2022-07-12
发明人： Jiseok HONG , Sung-Jin YEO , Yoongi HONG
IPC分类号： H01L27/108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10823 , H01L27/10894
摘要： A semiconductor device includes a substrate including cell and core regions respectively having first and second active patterns having respective, opposing sidewall surfaces at least partially defining a trench therebetween, and a boundary region between the cell and core regions, a device isolation layer on the boundary region to fill the trench, a line structure on the first active pattern and extended from the cell region to the boundary region, and a capping pattern covering an end of the line structure on the boundary region. The device isolation layer includes one or more inner surfaces at least partially defining a recess region, which is adjacent to the end of the line structure, and the capping pattern is extended along the end of the line structure into the recess region. A top surface of the device isolation layer is between the line structure and a bottom surface of the capping pattern.
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公开(公告)号：US20220130801A1
公开(公告)日：2022-04-28
申请号：US17568558
申请日：2022-01-04
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/538 , H01L23/31 , H01L23/16
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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公开(公告)号：US20210151410A1
公开(公告)日：2021-05-20
申请号：US17036508
申请日：2020-09-29
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
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公开(公告)号：US20210028152A1
公开(公告)日：2021-01-28
申请号：US16833761
申请日：2020-03-30
发明人： Hyuekjae LEE , Jihoon KIM , Jihwan SUH , Soyoun LEE , Jiseok HONG , Taehun KIM , Jihwan HWANG
IPC分类号： H01L25/065 , H01L23/00 , H01L23/16 , H01L23/31 , H01L23/538
摘要： Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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公开(公告)号：US20230232616A1
公开(公告)日：2023-07-20
申请号：US18186593
申请日：2023-03-20
发明人： Jiseok HONG , Sangho Lee , Seoryong Park , Jiyoung Ahn , Kiseok Lee , Kiseok Lee , Yoonyoung Choi , Seunguk Han
IPC分类号： H10B12/00
CPC分类号： H10B12/485 , H10B12/315 , H10B12/0335 , H10B12/482
摘要： An integrated circuit device includes: a substrate including a plurality of active regions; a bit line extending on the substrate in a horizontal direction; a direct contact connected between a first active region selected among the plurality of active regions and the bit line; an inner oxide layer contacting a sidewall of the direct contact; and a carbon-containing oxide layer nonlinearly extending on a sidewall of the bit line in a vertical direction, the carbon-containing oxide layer contacting the sidewall of the bit line.
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公开(公告)号：US20220344308A1
公开(公告)日：2022-10-27
申请号：US17861580
申请日：2022-07-11
发明人： Jihwan HWANG , Taehun KIM , Jihwan SUH , Soyoun LEE , Hyuekjae LEE , Jiseok HONG
IPC分类号： H01L25/065 , H01L25/00
摘要： A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.
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公开(公告)号：US20190221475A1
公开(公告)日：2019-07-18
申请号：US16106266
申请日：2018-08-21
发明人： Jiseok HONG , Kiseok LEE , Jemin PARK , Yoosang HWANG
IPC分类号： H01L21/768 , H01L23/532
CPC分类号： H01L21/76831 , H01L21/7682 , H01L21/76835 , H01L23/5222 , H01L23/53238 , H01L23/53295
摘要： A semiconductor device includes an interlayer insulation layer on a semiconductor substrate, a via plug and a wiring line on the via plug, in the interlayer insulation layer, the via plug and the wiring line coupled with each other and forming a stepped structure. The semiconductor device includes a first air-gap region between the interlayer insulation layer and the via plug, and a second air-gap region between the interlayer insulation layer and the wiring line. The first air-gap region and the second air-gap region are not vertically overlapped with each other.
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