公开(公告)号：US20220285312A1

公开(公告)日：2022-09-08

申请号：US17804110

申请日：2022-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan HWANG ,  Unbyoung KANG ,  Sangsick PARK ,  Jihwan SUH ,  Soyoun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.

公开(公告)号：US20230121888A1

公开(公告)日：2023-04-20

申请号：US17884695

申请日：2022-08-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsoo KIM ,  Jiho KIM ,  Unbyoung KANG ,  Sangsick PARK ,  Teakhoon LEE

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00

Abstract: A semiconductor package includes a first semiconductor chip including upper signal pads and upper dummy pads. A second semiconductor chip is on the first semiconductor chip, and includes lower signal pads and lower dummy pads. First conductive bumps are between the upper signal pads and the lower signal pads. Second conductive bumps are between the upper dummy pads and the lower dummy pads. The upper dummy pads include merged pads covering a plurality of adjacent lower dummy pads. A plurality of metal plating layers are disposed on each of the merged pads in areas respectively corresponding to the plurality of adjacent lower dummy pads. The second conductive bumps include a plurality of conductive bumps respectively disposed between the plurality of first metal plating layers and the plurality of adjacent lower dummy pads.

公开(公告)号：US20240421012A1

公开(公告)日：2024-12-19

申请号：US18210134

申请日：2023-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangsick PARK ,  Chungsun LEE ,  Hanmin LEE ,  Seungyoon JUNG

IPC: H01L23/24 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor device includes a first semiconductor chip having a first through silicon via (TSV). A second semiconductor chip is arranged on the first semiconductor chip and includes a second TSV positioned on a same vertical line as the first TSV. A conductive pad is disposed on each of the first TSV and the second TSV. The conductive pad electrically connects the first semiconductor chip and the second semiconductor chip to each other. A warpage prevention metal structure is disposed on an upper surface of the first semiconductor chip or an upper surface of the second semiconductor chip.

公开(公告)号：US20230420336A1

公开(公告)日：2023-12-28

申请号：US18085859

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonho JUN ,  Sangsick PARK ,  Chungsun LEE ,  Hyoungjoo LEE

IPC: H01L23/42 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/42 ,  H01L23/49833 ,  H01L23/49816 ,  H01L23/3157 ,  H01L24/16 ,  H01L24/81 ,  H01L21/56 ,  H01L2224/16227 ,  H01L2224/81

Abstract: A fan-out type semiconductor package is provided and may include: a package substrate; an interposer on an upper surface of the package substrate, the interposer including upper pads and lower pads electrically connected with the upper pads; conductive bumps between the package substrate and the lower pads of the interposer and electrically connecting the package substrate with the interposer; a semiconductor chip on a central portion of an upper surface of the interposer and electrically connected with the upper pads of the interposer; a molding member on an edge portion of the upper surface of the interposer, the molding member including an upper surface coplanar with an upper surface of the semiconductor chip; and a metal pillar structure vertically extending from the upper surface of the molding member to a lower surface of the interposer and configured to individually make contact with the lower pads of the interposer.

公开(公告)号：US20210375823A1

公开(公告)日：2021-12-02

申请号：US17142133

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihwan HWANG ,  Unbyoung KANG ,  Sangsick PARK ,  Jihwan SUH ,  Soyoun LEE ,  Teakhoon LEE

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.