公开(公告)号：US20220197510A1

公开(公告)日：2022-06-23

申请号：US17395582

申请日：2021-08-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngmin Lee ,  Changjun Lee ,  Jinmyung Yoon ,  Gyuseok Choe ,  Seongwan Hong

IPC: G06F3/06

Abstract: An operating method of a storage device, including a core and a memory, includes receiving a first processing code configured to enable execution of a first task and storing the first processing code in a first logical unit separately allocated in the memory for near-data processing (NDP), in response to a write command received from a host device, activating the core for executing the first processing code, in response to an activation command received from the host device, and executing the first task by using the core, in response to an execution command received from the host device.

公开(公告)号：US12019581B2

公开(公告)日：2024-06-25

申请号：US17936995

申请日：2022-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjin Kim ,  Jinmyung Yoon ,  Youngmin Lee ,  Dasom Lee

IPC: G06F15/80 ,  G06F12/02 ,  G06F12/0806 ,  G06F12/1045 ,  G06F13/16 ,  G06F15/163 ,  G06F15/167

CPC classification number: G06F15/80 ,  G06F12/023 ,  G06F12/0284 ,  G06F12/0806 ,  G06F12/1054 ,  G06F13/1663 ,  G06F15/163 ,  G06F15/167 ,  G06F2212/68

Abstract: A multi-core processor includes a plurality of cores, a shared memory, a plurality of address allocators, and a bus. The shared memory has a message queue including a plurality of memory regions for transmitting messages between the plurality of cores. The plurality of address allocators are configured to, each time addresses in a predetermined range corresponding to a reference memory region among the plurality of memory regions are received from a corresponding core among the plurality of cores, control the plurality of memory regions to be accessed in sequence by applying an offset determined according to an access count of the reference memory region to the addresses in the predetermined range. The bus is configured to connect the plurality of cores, the shared memory, and the plurality of address allocators to one another.

公开(公告)号：US20230195688A1

公开(公告)日：2023-06-22

申请号：US17936995

申请日：2022-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyungjin KIM ,  Jinmyung Yoon ,  Yongmin Lee ,  Dasom Lee

IPC: G06F15/80 ,  G06F12/02 ,  G06F12/1045

CPC classification number: G06F15/80 ,  G06F12/023 ,  G06F12/1054 ,  G06F2212/68

Abstract: A multi-core processor includes a plurality of cores, a shared memory, a plurality of address allocators, and a bus. The shared memory has a message queue including a plurality of memory regions for transmitting messages between the plurality of cores. The plurality of address allocators are configured to, each time addresses in a predetermined range corresponding to a reference memory region among the plurality of memory regions are received from a corresponding core among the plurality of cores, control the plurality of memory regions to be accessed in sequence by applying an offset determined according to an access count of the reference memory region to the addresses in the predetermined range. The bus is configured to connect the plurality of cores, the shared memory, and the plurality of address allocators to one another.