公开(公告)号：US10032890B2

公开(公告)日：2018-07-24

申请号：US15361516

申请日：2016-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Hwan Yim ,  Yeon-Tack Ryu ,  Joo-Cheol Han ,  Ja-Eung Koo ,  No-Ul Kim ,  Ho-Young Kim ,  Bo-Un Yoon

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51

Abstract: Disclosed is a method of manufacturing semiconductor devices. A gate trench and an insulation pattern defined by the gate trench are formed on a substrate and the protection pattern is formed on the insulation pattern. A gate dielectric layer, a work function metal layer and a sacrificial layer are sequentially formed the substrate along a surface profile of the gate trench. A sacrificial pattern is formed by a CMP while not exposing the insulation pattern. A residual sacrificial pattern is formed at a lower portion of the gate trench and the gate dielectric layer and the work function metal layer is etched into a gate dielectric pattern and a work function metal pattern using the residual sacrificial pattern as an etch stop layer.