公开(公告)号：US09684552B2

公开(公告)日：2017-06-20

申请号：US14680502

申请日：2015-04-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Hye Park ,  Jun-Ho Shin

IPC: G11C11/00 ,  G06F11/00 ,  G11C16/34 ,  G06F12/02

CPC classification number: G06F11/00 ,  G06F12/0246 ,  G06F2212/1032 ,  G11C16/3459

Abstract: A method for driving a nonvolatile memory device using a resistive element is provided. The method includes storing data in a page buffer, the data including a first data block and a second data block, writing the first data block to a memory cell, performing a verify-read operation on the first data block of the memory cell region, writing the second data block to the memory cell region, and performing a verify-read operation on the second data block of the memory cell region, wherein the first data block and the second data block are smaller than the page buffer in size.

公开(公告)号：US11114160B2

公开(公告)日：2021-09-07

申请号：US17034254

申请日：2020-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Venkataramana Gangasani ,  Moo-Sung Kim ,  Tae-Hui Na ,  Jun-Ho Shin

IPC: G11C13/00

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.

公开(公告)号：US10825517B2

公开(公告)日：2020-11-03

申请号：US16430657

申请日：2019-06-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Venkataramana Gangasani ,  Moo-Sung Kim ,  Tae-Hui Na ,  Jun-Ho Shin

IPC: G11C13/00

Abstract: A memory device includes a memory cell array including a plurality of memory cells arranged at points where a plurality of word lines and a plurality of bit lines intersect; a sense amplifier configured to amplify, in a read operation mode of the memory device, a voltage difference value between a voltage of a selected word line connected to a selected memory cell of the plurality of memory cells and a reference voltage; and a leakage current compensation circuit connected to a selected word line path between the selected memory cell and the sense amplifier and configured to compensate for a total leakage current generated by unselected memory cells connected to the selected word line in the read operation mode.