公开(公告)号：US20250048696A1

公开(公告)日：2025-02-06

申请号：US18609885

申请日：2024-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KI HWAN KIM ,  Unki Kim ,  Chanyoung Kim ,  Jeongho Yoo ,  Ingyu Jang ,  Sujin Jung

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and vertically spaced apart, a source/drain pattern on the active pattern, and a gate electrode on the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern, where the source/drain pattern includes a buffer layer and a main layer on the buffer layer, the main layer includes silicon that is doped with an impurity, an impurity concentration of the main layer is a first atomic fraction at a first level corresponding to the first semiconductor pattern, and the impurity concentration of the main layer is a second atomic fraction at a second level corresponding to the second semiconductor pattern.

公开(公告)号：US20230402535A1

公开(公告)日：2023-12-14

申请号：US18081855

申请日：2022-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNGHO KIM ,  KI HWAN KIM ,  KANG HUN MOON ,  CHOEUN LEE ,  YONGUK JEON

IPC: H01L29/775 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/775 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/41775

Abstract: A semiconductor device includes; a substrate including an active pattern, a channel pattern on the active pattern, the channel pattern including a plurality of spaced apart and vertically stacked semiconductor patterns, a source/drain pattern connected to the plurality of semiconductor patterns, a gate electrode on the plurality of semiconductor patterns, the gate electrode including a portion interposed between adjacent ones of the plurality of semiconductor patterns, and an inner spacer interposed between the portion of the gate electrode and the source/drain pattern, wherein the inner spacer is crystalline metal oxide is expressed by a formula (MO), wherein (O) is an oxygen atom, and (M) is a metal atom selected from a group consisting of Mg, Be, and Ga.