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公开(公告)号:US12046682B2
公开(公告)日:2024-07-23
申请号:US17689322
申请日:2022-03-08
发明人: Ingyu Jang , Jinbum Kim , Dahye Kim , Sujin Jung , Dongsuk Shin
IPC分类号: H01L29/78 , H01L21/02 , H01L21/764 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/423 , H01L29/66 , H01L29/786
CPC分类号: H01L29/78696 , H01L21/0259 , H01L21/764 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/0665 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/78618
摘要: An integrated circuit (IC) device includes a fin-type active region on a substrate. A mesa-type channel region protrudes from the fin-type active region in a vertical direction. The mesa-type channel region is integrally connected with the fin-type active region. A gate line substantially surrounds a mesa-type channel region on the fin-type active region. A gate dielectric film is between the mesa-type channel region and the gate line. The mesa-type channel region includes: a plurality of round convex portions, which are convex toward the gate line; a concavo-convex sidewall, which includes a portion of each of the plurality of round convex portions and faces the gate line; and at least one void, which is inside the mesa-type channel region.
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公开(公告)号:US11862733B2
公开(公告)日:2024-01-02
申请号:US17480457
申请日:2021-09-21
发明人: Sunguk Jang , Kihwan Kim , Sujin Jung , Youngdae Cho
IPC分类号: H01L29/786 , H01L29/08 , H01L29/423 , H01L29/78 , H01L29/06 , H01L29/66
CPC分类号: H01L29/78696 , H01L29/0673 , H01L29/0843 , H01L29/0847 , H01L29/4232 , H01L29/42392 , H01L29/66545 , H01L29/7851 , H01L29/7854
摘要: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.
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公开(公告)号:US11616144B2
公开(公告)日:2023-03-28
申请号:US16412796
申请日:2019-05-15
发明人: Sunguk Jang , Sujin Jung , Jinyeong Joe , Jeongho Yoo , Seung Hun Lee , Jongryeol Yoo
IPC分类号: H01L29/786 , H01L29/78 , H01L29/417 , H01L27/088 , H01L29/08 , H01L29/10 , H01L29/66
摘要: A semiconductor device includes a first active fin protruding from a substrate, a first gate pattern covering a side surface and a top surface of the first active fin, and first source/drain patterns at opposite sides of the first gate pattern, each of the first source/drain patterns including a first lower side and a second lower side spaced apart from each other, a first upper side extended from the first lower side, a second upper side extended from the second lower side. The first lower side may be inclined at a first angle relative to a top surface of the substrate, the second upper side may be inclined at a second angle relative to the top surface of the substrate, and the first angle may be greater than the second angle.
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公开(公告)号:US11195954B2
公开(公告)日:2021-12-07
申请号:US16732864
申请日:2020-01-02
发明人: Youngdae Cho , Sunguk Jang , Sujin Jung , Jungtaek Kim , Sihyung Lee
IPC分类号: H01L29/78 , H01L29/423
摘要: A semiconductor device may include semiconductor patterns, a gate structure, a first spacer, a first semiconductor layer and a second semiconductor layer. The semiconductor patterns may be formed on a substrate, and may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate and may overlap in the vertical direction. The gate structure may be formed on the substrate and the semiconductor patterns. At least portion of the gate structure may be formed vertically between the semiconductor patterns. The first spacer may cover opposite sidewalls of the gate structure, the sidewalls opposite to each other in a first direction. The first semiconductor layer may cover the sidewalls of the semiconductor patterns in the first direction, and surfaces of the first spacer and the substrate. The first semiconductor layer may have a first concentration of impurities. The second semiconductor layer may be formed on the first semiconductor layer, and may have a second concentration of impurities different from the first concentration of impurities. The semiconductor device may have good characteristics and high reliability.
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公开(公告)号:US11177346B2
公开(公告)日:2021-11-16
申请号:US16666958
申请日:2019-10-29
发明人: Ki Hwan Kim , Sunguk Jang , Pankwi Park , Sangmoon Lee , Sujin Jung
摘要: A semiconductor device including an active fin that protrudes from a substrate and forms a plurality of recess regions spaced apart from each other, a gate pattern between the plurality of recess regions that covers a lateral surface and a top surface of the active fin, a plurality of source/drain patterns in the plurality of recess regions, and a diffusion reduction region adjacent to each of a plurality of bottoms of the plurality of recess regions and each of a plurality of sidewalls of the plurality of recess regions, the diffusion reduction region including a dopant having a lower diffusion coefficient than phosphorus (P).
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公开(公告)号:US20200381563A1
公开(公告)日:2020-12-03
申请号:US16734537
申请日:2020-01-06
发明人: Sunguk Jang , Kihwan Kim , Sujin Jung , Youngdae Cho
IPC分类号: H01L29/786 , H01L29/78 , H01L29/423 , H01L29/08
摘要: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.
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公开(公告)号:US20200381562A1
公开(公告)日:2020-12-03
申请号:US16715431
申请日:2019-12-16
发明人: Sujin Jung , Junbeom Park , Kihwan Kim , Sunguk Jang , Youngdae Cho
IPC分类号: H01L29/786 , H01L29/06 , H01L29/423 , H01L21/02 , H01L29/66
摘要: A semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.
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公开(公告)号:US20190252526A1
公开(公告)日:2019-08-15
申请号:US16116577
申请日:2018-08-29
发明人: Jongryeol Yoo , Jeongho Yoo , Sujin Jung , Youngdae Cho
IPC分类号: H01L29/66 , H01L29/10 , H01L21/8234 , H01L29/78 , H01L21/02 , H01L21/8238
摘要: A semiconductor device includes a well region in a substrate, a semiconductor pattern on the well region, the semiconductor pattern including an impurity, and a gate electrode on the semiconductor pattern. A concentration of the impurity in the semiconductor pattern increases in a direction from an upper portion of the semiconductor pattern, adjacent to the gate electrode, to a lower portion of the semiconductor pattern, adjacent to the well region.
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公开(公告)号:US20160027902A1
公开(公告)日:2016-01-28
申请号:US14805876
申请日:2015-07-22
发明人: Jieon Yoon , Seokhoon Kim , Gyeom Kim , Nam-Kyu Kim , JinBum Kim , Dong Chan Suh , Kwan Heum Lee , Byeongchan Lee , Choeun Lee , Sujin Jung
CPC分类号: H01L29/66795 , H01L21/26506 , H01L21/30608 , H01L21/3247 , H01L21/823425 , H01L29/045 , H01L29/0847 , H01L29/165 , H01L29/6656 , H01L29/66636 , H01L29/7848
摘要: Provided is a method of fabricating a semiconductor device. The method includes forming a gate pattern on a semiconductor substrate, injecting amorphization elements into the semiconductor substrate to form an amorphous portion at a side of the gate pattern, removing the amorphous portion to form a recess region, and forming a source/drain pattern in the recess region. When the recess region is formed, an etch rate of the amorphous portion is substantially the same in two different directions (e.g., and any other direction) of the semiconductor substrate.
摘要翻译: 提供一种制造半导体器件的方法。 该方法包括在半导体衬底上形成栅极图案,将非晶化元件注入到半导体衬底中以在栅极图案的一侧形成非晶部分,去除非晶部分以形成凹陷区域,并且形成源极/漏极图案 凹陷区域。 当形成凹陷区域时,非晶部分的蚀刻速率在半导体衬底的两个不同方向(例如,<111>和任何其它方向)上基本相同。
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公开(公告)号:US20240321885A1
公开(公告)日:2024-09-26
申请号:US18476688
申请日:2023-09-28
发明人: Jinbum Kim , Ingyu Jang , Sujin Jung , Gyeom Kim , Hyojin Kim , Yongjun Nam , Sangmoon Lee
IPC分类号: H01L27/092 , H01L21/8238
CPC分类号: H01L27/092 , H01L21/823814 , H01L21/823871
摘要: An integrated circuit device includes a first transistor comprising a first conductivity type, which includes a first channel region and a first source/drain region, a second transistor comprising a second conductivity type, which includes a second channel region and a second source/drain region, a first contact structure that contacts the first source/drain region and comprising a first length, and the first contact structure extends from above the first source/drain region and beyond an uppermost surface of the first channel region by a first vertical distance, and a second contact structure that contacts the second source/drain region and having a second length that is greater than the first length, the second contact extends from above the second source/drain region and beyond an uppermost surface of the second channel region by a second vertical distance, which is greater than the first vertical distance.
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