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公开(公告)号：US20250081469A1
公开(公告)日：2025-03-06
申请号：US18812283
申请日：2024-08-22
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KIJOON KIM , TAEYOUNG KIM , SUHWAN LIM
Abstract: A vertical semiconductor device includes: a plurality of insulation patterns on a substrate, the plurality of insulation patterns being spaced apart from each other in a vertical direction; a plurality of channel structures being spaced apart from each other in a first direction, each of the plurality of channel structures including interface insulation patterns, and the plurality of channel structures disposed in a first trench extending in the first direction and passing through the insulation patterns in the vertical direction; a ferroelectric structure on an outer surface of each of the plurality channel structures, the ferroelectric structure protruding in a direction toward a gap between some of the insulation patterns in the vertical direction; and a conductive pattern on a sidewall of the ferroelectric structure, the conductive pattern filling the gap in the vertical direction.
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公开(公告)号：US20230413524A1
公开(公告)日：2023-12-21
申请号：US18186849
申请日：2023-03-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： KIJOON KIM
CPC classification number: H10B12/315 , H10B12/482 , H10B12/488 , H01L29/78391
Abstract: A semiconductor device includes bit lines arranged on a substrate and extending in a first horizontal direction; channel layers respectively arranged on the plurality of bit lines; word lines respectively arranged on the plurality of channel layers, and extending in a second horizontal direction; and ferroelectric layers arranged between the plurality of channel layers and the plurality of word lines, wherein the plurality of ferroelectric layers comprise a base dielectric layer and a nanoparticle, the nanoparticle dispersed and arranged in the base dielectric layer, respectively, the nanoparticle has a core-shell structure including a core and a shell.
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