公开(公告)号：US20150043295A1

公开(公告)日：2015-02-12

申请号：US14336337

申请日：2014-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-JEONG KIM ,  HEON LEE ,  HOON-CHANG YANG ,  KWANG-WOO LEE

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/02 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract translation: 提供了一种刷新易失性存储器的方法。 该方法包括根据短于刷新周期的弱小区刷新周期来存储关于要更新的​​弱小区行地址的地址信息，执行用于生成刷新行地址的计数操作，将刷新行地址与 地址信息，当比较结果表明地址信息的刷新行地址和弱单元行地址彼此一致时，刷新弱单元行地址，通过改变地址信息的指针来改变弱单元行地址 ，并且根据弱小区刷新周期刷新改变的弱小区行地址。

公开(公告)号：US20250095732A1

公开(公告)日：2025-03-20

申请号：US18624884

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUDONG PARK ,  SEULJI SONG ,  KWANG-WOO LEE

IPC: G11C13/00

Abstract: A memory device includes word lines, bit lines, memory cells, and a circuit. The circuit applies a first voltage to a first bit line of a target memory cell, applies a second voltage to a first word line of the target memory cell, and performs at least one of a first operation and a second operation. The first operation includes applying an adjustment voltage to a second bit line or second word line connected to an adjacent initialized memory cell, and the second operation includes applying a third voltage of an opposite polarity to the first voltage to a third bit line of a next target memory cell that is initialized after initialization of the target memory cell and applying a fourth voltage of an opposite polarity to the second voltage to a third word line of the next target memory cell.

公开(公告)号：US20190181342A1

公开(公告)日：2019-06-13

申请号：US16277685

申请日：2019-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-WOO LEE ,  DAE-HWAN KANG ,  GWAN-HYEOB KOH

IPC: H01L45/00 ,  H01L27/24

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.

公开(公告)号：US20170271592A1

公开(公告)日：2017-09-21

申请号：US15366574

申请日：2016-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANG-WOO LEE ,  DAE-HWAN KANG ,  GWAN-HYEOB KOH

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1675 ,  H01L27/2427 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: The semiconductor device includes a plurality of first conductive patterns on a substrate, a first selection pattern on each of the plurality of first conductive patterns, a first structure on the first selection pattern, a plurality of second conductive patterns on the first structures, a second selection pattern on each of the plurality of second conductive patterns, a second structure on the second selection pattern, and a plurality of third conductive patterns on the second structures. Each of the plurality of first conductive patterns may extend in a first direction. The first structure may include a first variable resistance pattern and a first heating electrode. The first variable resistance pattern and the first heating electrode may contact each other to have a first contact area therebetween. Each of the plurality of second conductive patterns may extend in a second direction crossing the first direction. The second structure may include a second variable resistance pattern and a second heating electrode. The second variable resistance pattern and the second heating electrode may contact each other to have a second contact area therebetween, and the second contact area may be different from the first contact area.