公开(公告)号：US20210374001A1

公开(公告)日：2021-12-02

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  DEOKHO SEO ,  WONJAE SHIN ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20220366949A1

公开(公告)日：2022-11-17

申请号：US17535861

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  DEOKHO SEO ,  INSU CHOI

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

公开(公告)号：US20150043295A1

公开(公告)日：2015-02-12

申请号：US14336337

申请日：2014-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-JEONG KIM ,  HEON LEE ,  HOON-CHANG YANG ,  KWANG-WOO LEE

IPC: G11C11/406

CPC classification number: G11C11/406 ,  G11C11/40615 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/02 ,  G11C2211/4065 ,  G11C2211/4068

Abstract: A method is provided for refreshing a volatile memory. The method includes storing address information about a weak cell row address that is to be refreshed according to a weak cell refresh period that is shorter than a refresh period, performing a counting operation for generating a refresh row address, comparing the refresh row address with the address information, refreshing the weak cell row address when a result of the comparison shows that the refresh row address and the weak cell row address of the address information coincide with each other, changing the weak cell row address by changing a pointer of the address information, and refreshing the changed weak cell row address according to the weak cell refresh period.

Abstract translation: 提供了一种刷新易失性存储器的方法。 该方法包括根据短于刷新周期的弱小区刷新周期来存储关于要更新的​​弱小区行地址的地址信息，执行用于生成刷新行地址的计数操作，将刷新行地址与 地址信息，当比较结果表明地址信息的刷新行地址和弱单元行地址彼此一致时，刷新弱单元行地址，通过改变地址信息的指针来改变弱单元行地址 ，并且根据弱小区刷新周期刷新改变的弱小区行地址。

公开(公告)号：US20210373995A1

公开(公告)日：2021-12-02

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  MINSU KIM ,  DEOKHO SEO ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/16

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

公开(公告)号：US20180173595A1

公开(公告)日：2018-06-21

申请号：US15805622

申请日：2017-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-JEONG KIM ,  YOENHWA LEE

IPC: G06F11/14

CPC classification number: G06F11/1458 ,  G06F11/1448 ,  G11C14/0018 ,  G11C17/16 ,  G11C29/00 ,  G11C29/42 ,  G11C29/4401 ,  G11C2029/0407 ,  G11C2029/4402 ,  G11C2229/743

Abstract: A data backup method for performing a post package repair (PPR) operation includes reading repair unit information of a memory device, storing the repair unit information in a register, determining whether to perform the PPR operation in response to a read error occurring while the memory device is being accessed, and performing a data backup operation of the memory device based on the repair unit information in response to determining that the PPR operation is to be performed.