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    INTEGRATED CIRCUIT INCLUDING LOAD STANDARD CELL AND METHOD OF DESIGNING THE SAME
    4.
    发明申请
    INTEGRATED CIRCUIT INCLUDING LOAD STANDARD CELL AND METHOD OF DESIGNING THE SAME 审中-公开

    公开(公告)号：US20190197214A1

    公开(公告)日：2019-06-27

    申请号：US16164055

    申请日：2018-10-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kwan-Yeob Chae ,  Jong-Ryun Choi

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5059 ,  G06F17/5072

    摘要： To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

    Integrated circuit including load standard cell and method of designing the same
    6.
    发明授权
    Integrated circuit including load standard cell and method of designing the same 有权

    公开(公告)号：US10977412B2

    公开(公告)日：2021-04-13

    申请号：US16164055

    申请日：2018-10-18

    申请人： Samsung Electronics Co., Ltd.

    发明人： Kwan-Yeob Chae ,  Jong-Ryun Choi

    IPC分类号： G06F17/50 ,  G06F30/394 ,  G06F30/35 ,  G06F30/392

    摘要： To design an integrated circuit, input data defining an integrated circuit are received, and a plurality of load standard cells having different delay characteristics are provided in a standard cell library. Placement and routing are performed based on the input data and the standard cell library and output data defining the integrated circuit are generated based on a result of the placement and the routing. Design efficiency and performance of the integrated circuit are enhanced by designing the integrated circuit with delay matching and duty ratio adjustment using the load standard cell.

    Delay cell and delay line having the same
    7.
    发明授权
    Delay cell and delay line having the same 有权

    公开(公告)号：US09859880B2

    公开(公告)日：2018-01-02

    申请号：US15290076

    申请日：2016-10-11

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Kwan-Yeob Chae ,  Sang-Hoon Joo ,  Sang-Hune Park ,  Jong-Ryun Choi ,  Hoon-Koo Lee

    IPC分类号： H03K5/13 ,  H03K19/20 ,  H03K5/134 ,  H03K5/00

    CPC分类号： H03K5/13 ,  H03K5/134 ,  H03K19/20 ,  H03K2005/00032

    摘要： A delay cell includes first through fifth inversion circuits. The first inversion circuit inverts an input signal, and an output electrode of the first inversion circuit is coupled to a first node. The second inversion circuit is turned on in response to a control signal, and inverts the input signal when turned on. An output electrode of the second inversion circuit is coupled to the first node. The third inversion circuit inverts a signal at the first node, and an output electrode of the third inversion circuit is coupled to a second node. The fourth inversion circuit is turned on in response to the control signal, and inverts the signal at the first node when turned on. An output electrode of the fourth inversion circuit is coupled to the second node. The fifth inversion circuit inverts a signal at the second node to generate an output signal.