Dual-edge-triggered flip-flop
    1.
    发明授权

    公开(公告)号:US12218669B2

    公开(公告)日:2025-02-04

    申请号:US18330731

    申请日:2023-06-07

    Abstract: A flip-flop includes an input logic circuit, a first latch, a second latch, and an output multiplexer; where the input logic circuit outputs a clock bar signal based on an input data bit and a clock signal, where the first latch and the second latch operate based on the input data bit, the clock signal, and a clock bar signal, where the output multiplexer operates based on outputs from nodes of the first and second nodes and outputs an output data bit, and where the input logic circuit has a uniform value in a period where there is no change of a value of the output data bit.

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