公开(公告)号：US20210343347A1

公开(公告)日：2021-11-04

申请号：US17375206

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Won Yun ,  Kyung Min Kang ,  Dong Ku Kang

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

公开(公告)号：US11670377B2

公开(公告)日：2023-06-06

申请号：US17375206

申请日：2021-07-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Won Yun ,  Kyung Min Kang ,  Dong Ku Kang

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

CPC classification number: G11C16/24 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.

公开(公告)号：US11114167B2

公开(公告)日：2021-09-07

申请号：US16662247

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Won Yun ,  Kyung Min Kang ,  Dong Ku Kang

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/10 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11519

Abstract: Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.