公开(公告)号：US11830567B2

公开(公告)日：2023-11-28

申请号：US17372697

申请日：2021-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon Ma ,  Chunhyung Chung ,  Jamin Koo ,  Kyuwan Kim ,  Daeyoung Moon ,  Wonseok Yoo

IPC: G11C5/06 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H10B12/00

CPC classification number: G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/532 ,  H10B12/0335 ,  H10B12/315 ,  H10B12/482

Abstract: An integrated circuit device includes; word lines extending in a first direction across a substrate and spaced apart in a second direction different from the first direction, bit lines extending on the word lines in the second direction and spaced apart in the first direction, a first contact plug arranged among the bitlines, contacting a first active region of the substrate, having a first width, and having a first dopant concentration, and a second contact plug arranged among the bitlines, contacting a second active region of the substrate, having a second width, and having a second dopant concentration less than the first dopant concentration.

公开(公告)号：US11631677B2

公开(公告)日：2023-04-18

申请号：US17358055

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US12200922B2

公开(公告)日：2025-01-14

申请号：US18116883

申请日：2023-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H10B12/00

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.

公开(公告)号：US20240105791A1

公开(公告)日：2024-03-28

申请号：US18371869

申请日：2023-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung MOON ,  Jamin Koo ,  Kyuwan Kim ,  Jonghyeok Kim ,  Hyokyoung Kim ,  Kisoo Park

IPC: H01L29/423 ,  H10B12/00

CPC classification number: H01L29/4236 ,  H10B12/315 ,  H10B12/482 ,  H10B12/488

Abstract: An integrated circuit device includes a substrate including a plurality of active regions; a plurality of device isolation layers provided in the substrate and defining the plurality of active regions; a plurality of bitlines spaced apart from each other in a first horizontal direction on the substrate and extending in a second horizontal direction crossing the first horizontal direction; a plurality of insulating fences spaced apart from each other in the second horizontal direction and provided between adjacent bitlines of the plurality of bitlines; a plurality of buried contacts connected to the plurality of active regions and provided between adjacent bitlines of the plurality of bitlines and between the plurality of insulating fences; and a plurality of vertical insulating layers vertically positioned between the plurality of insulating fences and the plurality of buried contacts.

公开(公告)号：US20220173107A1

公开(公告)日：2022-06-02

申请号：US17358055

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daeyoung Moon ,  Jamin Koo ,  Kyuwan Kim ,  Kisoo Park

IPC: H01L27/108

Abstract: A semiconductor memory device includes a device isolation pattern on a substrate to define an active region, a word line in the substrate, to intersect the active region, a first dopant region in the active region as at a first side of the word line, a second dopant region in the active region at a second side of the word line, a bit line connected to the first dopant region and intersecting the word line, a bit line contact connecting the bit line to the first dopant region, a landing pad on the second dopant region, and a storage node contact connecting the landing pad to the second dopant region, the storage node contact including a first portion in contact with the second dopant region, the first portion including a single-crystal silicon, and a second portion on the first portion and including a poly-silicon.