公开(公告)号：US20240292608A1

公开(公告)日：2024-08-29

申请号：US18659188

申请日：2024-05-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong PARK ,  Jae-Wha PARK ,  Moon Keun KIM ,  Jung Ha HWANG

IPC: H10B12/00 ,  G11C5/06

CPC classification number: H10B12/50 ,  H10B12/33 ,  G11C5/063

Abstract: A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.

公开(公告)号：US20220102358A1

公开(公告)日：2022-03-31

申请号：US17461051

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hong PARK ,  Jae-Wha PARK ,  Moon Keun KIM ,  Jung Ha HWANG

IPC: H01L27/108

Abstract: A semiconductor memory device may include at least one semiconductor pattern including a horizontal portion extending in a second direction parallel to a top surface of a semiconductor substrate and a vertical portion extending in the first direction, at least one gate electrode on the horizontal portion of the at least one semiconductor pattern and extending in a third direction different from the first direction and the second direction, and at least one information storage element connected to the vertical portion of the at least one semiconductor pattern, wherein a thickness of the horizontal portion of the at least one semiconductor pattern in the first direction is smaller than a thickness of the vertical portion of the at least one semiconductor pattern in the first direction.

公开(公告)号：US20210242079A1

公开(公告)日：2021-08-05

申请号：US17215365

申请日：2021-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Keun KIM ,  Jae Wha PARK ,  Jun Kwan KIM ,  Hyo Jeong MOON ,  Seung Jong PARK ,  Seul Gi BAE

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/02 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.

公开(公告)号：US20200027783A1

公开(公告)日：2020-01-23

申请号：US16271120

申请日：2019-02-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Moon Keun KIM ,  Jae Wha PARK ,  Jun Kwan KIM ,  Hyo Jeong MOON ,  Seung Jong PARK ,  Seul Gi BAE

IPC: H01L21/768 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

Abstract: A method for fabricating a semiconductor device includes forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate, forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer, and forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas containing deuterium and a second gas containing hydrogen.