公开(公告)号：US20240113077A1

公开(公告)日：2024-04-04

申请号：US18230768

申请日：2023-08-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nara LEE ,  Yeonjin LEE ,  Jimin CHOI ,  Jongmin LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/481 ,  H01L24/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A semiconductor package includes a plurality of first semiconductor chips sequentially stacked, each of the first semiconductor chips including a circuit layer on a first surface of a first substrate, a through-silicon via passing through the first substrate, and a bump pad connected to the through-silicon via, and a second semiconductor chip on an uppermost first semiconductor chip, the second semiconductor chip including a circuit layer on a first surface of a second substrate, and a thermal path via in the second substrate.

公开(公告)号：US20240071923A1

公开(公告)日：2024-02-29

申请号：US18209820

申请日：2023-06-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun SONG ,  Jongmin LEE ,  Joongwon SHIN ,  Nara LEE ,  Jimin CHOI

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/53295 ,  H01L24/16 ,  H01L25/0657 ,  H10B80/00 ,  H01L23/53228 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.