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公开(公告)号：US20170125283A1
公开(公告)日：2017-05-04
申请号：US15334469
申请日：2016-10-26
发明人： Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC分类号： H01L21/768 , H01L23/532 , H01L23/535
CPC分类号： H01L21/7682 , H01L21/76805 , H01L21/76849 , H01L21/76895 , H01L23/5329 , H01L23/535 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876
摘要： According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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公开(公告)号：US20240290677A1
公开(公告)日：2024-08-29
申请号：US18459111
申请日：2023-08-31
发明人： Gyuseong PARK , Joongwon SHIN , Jong-Min LEE , Jimin CHOI
IPC分类号： H01L23/31 , H01L21/56 , H01L21/768 , H01L23/00 , H01L23/532
CPC分类号： H01L23/3157 , H01L21/56 , H01L21/76801 , H01L23/3192 , H01L23/53295 , H01L24/13 , H01L23/291 , H01L24/05 , H01L2224/05567 , H01L2224/05571 , H01L2224/05611 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05657 , H01L2224/05669 , H01L2224/05676 , H01L2224/05681 , H01L2224/05684 , H01L2224/05686 , H01L2224/13021 , H01L2224/13082 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/13169 , H01L2224/13176 , H01L2224/13181 , H01L2224/13184 , H01L2224/13186 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/0496
摘要： A semiconductor device includes an interlayer insulating layer, a first protective insulating layer on the interlayer insulating layer, a second protective insulating layer on the first protective insulating layer, and insulating structures disposed in at least one of the first protective insulating layer or the second protective insulating layer, wherein the insulating structures include a first insulating structure including a first material having a first physical property, and a second insulating structure including a second material having a second physical property, and the first material and the second material include a same material, and the first physical property and the second physical property are different physical properties.
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公开(公告)号：US20230078980A1
公开(公告)日：2023-03-16
申请号：US17696989
申请日：2022-03-17
发明人： Jimin CHOI , Jeonil LEE , Jongmin LEE , Juik LEE
IPC分类号： H01L25/065 , H01L23/367 , H01L23/42 , H01L23/48
摘要： A thermal pad of a semiconductor chip, a semiconductor chip including the thermal pad, and a method of manufacturing the semiconductor chip, the thermal pad including a thermal core in a trench at a lower surface of a semiconductor substrate, the thermal core being configured to receive heat generated from a through silicon via (TSV) vertically extending through the semiconductor substrate; a thermal head connected to the thermal core and protruding from the lower surface of the semiconductor substrate, the thermal head being configured to dissipate the heat in the thermal core; a first insulation layer between an inner surface of the trench and the thermal core; and a second insulation layer between the first insulation layer and the thermal core.
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公开(公告)号：US20230076238A1
公开(公告)日：2023-03-09
申请号：US17882748
申请日：2022-08-08
发明人： Junhyung KIM , Jong-Min LEE , Minjung CHOI , Jimin CHOI
IPC分类号： H01L23/528 , H01L23/00 , H01L21/822 , H01L25/065 , H01L21/66
摘要： Semiconductor chips, semiconductor packages, and semiconductor chip fabrication methods may be provided. The semiconductor chip includes a substrate including a device region and an edge region, a device layer and a wiring layer sequentially stacked on the substrate, a sub-pad on the device region and a residual test pattern on the edge region wherein a sidewall of the residual test pattern is aligned with a sidewall of the substrate, and an upper dielectric stack covering the sub-pad and the residual test pattern. The upper dielectric stack may expose a portion of a top surface of the residual test pattern. A sidewall of the upper dielectric stack may have a stepped region.
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公开(公告)号：US20240071923A1
公开(公告)日：2024-02-29
申请号：US18209820
申请日：2023-06-14
发明人： Minjun SONG , Jongmin LEE , Joongwon SHIN , Nara LEE , Jimin CHOI
IPC分类号： H01L23/528 , H01L23/00 , H01L23/522 , H01L23/532 , H01L25/065 , H10B80/00
CPC分类号： H01L23/5283 , H01L23/5226 , H01L23/53223 , H01L23/53266 , H01L23/53295 , H01L24/16 , H01L25/0657 , H10B80/00 , H01L23/53228 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2924/1431 , H01L2924/1436
摘要： A semiconductor device may include lower metal wirings on a substrate, a first upper insulating interlayer on the lower metal wirings, a first upper wiring including a first upper via in the first upper insulating interlayer and a first upper metal pattern on the first upper insulating interlayer. The semiconductor device may also include a second upper insulating interlayer on the first upper insulating interlayer, an uppermost wiring including an uppermost via in the second upper insulating interlayer, an uppermost metal pattern on the second upper insulating interlayer, and an oxide layer for supplying hydrogen on the second upper insulating interlayer. The lower metal wirings may be stacked in a plurality of layers. The oxide layer for supplying hydrogen may cover the uppermost wiring. A thickness of the uppermost via may be less than 40% of a thickness of the uppermost metal pattern.
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公开(公告)号：US20230043650A1
公开(公告)日：2023-02-09
申请号：US17964244
申请日：2022-10-12
发明人： Jihoon CHANG , Jimin CHOI , Yeonjin LEE , Hyeon-Woo JANG , Jung-Hoon HAN
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
摘要： The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.
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公开(公告)号：US20230030117A1
公开(公告)日：2023-02-02
申请号：US17714202
申请日：2022-04-06
发明人： Juik LEE , Jong-Min LEE , Jimin CHOI , Yeonjin LEE , Jeon Il LEE
IPC分类号： H01L23/48 , H01L23/522 , H01L23/528 , H01L25/065 , H01L23/00 , H01L25/10
摘要： A semiconductor device includes a substrate including a first side and a second side opposite to each other, a first penetrating structure that penetrates the substrate, and a second penetrating structure that penetrates the substrate, the second penetrating structure being spaced apart from the first penetrating structure, and an area of the first penetrating structure being more than twice an area of the second penetrating structure, as viewed from the first side of the substrate.
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公开(公告)号：US20210305153A1
公开(公告)日：2021-09-30
申请号：US17153963
申请日：2021-01-21
发明人： Jihoon CHANG , Jimin CHOI , Yeonjin LEE , Hyeon-Woo JANG , Jung-Hoon HAN
IPC分类号： H01L23/522 , H01L21/768 , H01L23/532
摘要： The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.
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公开(公告)号：US20210020495A1
公开(公告)日：2021-01-21
申请号：US17039431
申请日：2020-09-30
发明人： Myeong-Dong LEE , KEUNNAM KIM , Dongryul LEE , Minseong CHOI , Jimin CHOI , YONG KWAN KIM , CHANGHYUN CHO , YOOSANG HWANG
IPC分类号： H01L21/768 , H01L27/108 , H01L23/532 , H01L23/535
摘要： According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
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10.发明公开公开(公告)号：US20240332228A1
公开(公告)日：2024-10-03
申请号：US18535351
申请日：2023-12-11
发明人： Joongwon SHIN , Yeonjin LEE , Jongmin LEE , Jimin CHOI
IPC分类号： H01L23/00 , H01L23/31 , H01L23/48 , H01L23/522 , H01L25/065
CPC分类号： H01L24/05 , H01L23/3107 , H01L23/481 , H01L23/5226 , H01L24/16 , H01L25/0657 , H01L2224/02206 , H01L2224/05016 , H01L2224/05124 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/16145
摘要： A semiconductor device includes an insulating structure on a semiconductor substrate, lower conductive patterns in the insulating structure, upper conductive patterns on the insulating structure, conductive vias in the insulating structure and connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns, a protective layer covering the insulating structure and the upper conductive patterns, an etch stop layer covering the protective layer, a first passivation layer on portions of the etch stop layer between the upper conductive patterns, and an upper passivation layer on the first passivation layer.
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