公开(公告)号：US10403641B2

公开(公告)日：2019-09-03

申请号：US15987545

申请日：2018-05-23

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Sung-Gil Kim ,  Seul-Ye Kim ,  Hong-suk Kim ,  Phil-Ouk Nam ,  Jae-Young Ahn ,  Ji-Hoon Choi

IPC分类号： H01L29/792 ,  H01L27/11582 ,  H01L27/11556 ,  H01L21/768 ,  H01L21/311

摘要： A semiconductor device may include a plurality of conductive patterns and an insulation pattern. The plurality of conductive patterns may be formed on a substrate. The plurality of conductive patterns may be spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate. Each of the plurality of conductive patterns may have an extension portion and a step portion. The step portion may be disposed at an edge of the corresponding conductive pattern. The insulation pattern may be formed between the plurality of conductive patterns in the vertical direction. A lower surface and an upper surface of the step portion of each of the plurality of conductive patterns may be bent upwardly.

公开(公告)号：US09905568B2

公开(公告)日：2018-02-27

申请号：US15251580

申请日：2016-08-30

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yong-Hoon Son ,  Jong-Won Kim ,  Chang-Seok Kang ,  Young-Woo Park ,  Jae-Duk Lee ,  Kyung-Hyun Kim ,  Byeong-Ju Kim ,  Phil-Ouk Nam ,  Kwang-Chul Park ,  Yeon-Sil Sohn ,  Jin-I Lee ,  Won-Bong Jung

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC分类号： H01L27/1157 ,  H01L27/11565 ,  H01L27/11582 ,  H01L29/66833

摘要： A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.