公开(公告)号：US20230236836A1

公开(公告)日：2023-07-27

申请号：US18194174

申请日：2023-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUKHAN LEE ,  SHINHAENG KANG ,  NAMSUNG KIM ,  SEONGIL O ,  HAK-SOO YU

IPC: G06F9/30 ,  G06F9/32 ,  G06F15/78

CPC classification number: G06F9/30145 ,  G06F9/321 ,  G06F15/7821

Abstract: A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.

公开(公告)号：US20200294558A1

公开(公告)日：2020-09-17

申请号：US16813851

申请日：2020-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD,

Inventor： HAK-SOO YU ,  NAMSUNG KIM ,  KYOMIN SOHN ,  SEONGIL O ,  SUKHAN LEE

IPC: G11C7/10 ,  G11C11/409 ,  G11C11/408 ,  G11C5/02

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US20220036929A1

公开(公告)日：2022-02-03

申请号：US17504918

申请日：2021-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HAK-SOO YU ,  NAMSUNG KIM ,  KYOMIN SOHN ,  SEONGIL O ,  SUKHAN LEE

IPC: G11C7/10 ,  G11C5/02 ,  G11C11/408 ,  G11C11/409

Abstract: A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.

公开(公告)号：US20200294575A1

公开(公告)日：2020-09-17

申请号：US16810344

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONGIL O ,  SHINHAENG KANG ,  NAMSUNG KIM ,  KYOMIN SOHN ,  SUKHAN LEE

IPC: G11C11/4096 ,  G06F13/16 ,  G06N3/04 ,  G06N3/063

Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.