-
公开(公告)号：US20220036929A1
公开(公告)日：2022-02-03
申请号：US17504918
申请日：2021-10-19
发明人： HAK-SOO YU , NAMSUNG KIM , KYOMIN SOHN , SEONGIL O , SUKHAN LEE
IPC分类号： G11C7/10 , G11C5/02 , G11C11/408 , G11C11/409
摘要： A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.
-
公开(公告)号：US20200294575A1
公开(公告)日：2020-09-17
申请号：US16810344
申请日：2020-03-05
发明人： SEONGIL O , SHINHAENG KANG , NAMSUNG KIM , KYOMIN SOHN , SUKHAN LEE
IPC分类号： G11C11/4096 , G06F13/16 , G06N3/04 , G06N3/063
摘要： A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.
-
3.发明申请公开(公告)号：US20200294558A1
公开(公告)日：2020-09-17
申请号：US16813851
申请日：2020-03-10
发明人： HAK-SOO YU , NAMSUNG KIM , KYOMIN SOHN , SEONGIL O , SUKHAN LEE
IPC分类号： G11C7/10 , G11C11/409 , G11C11/408 , G11C5/02
摘要： A memory device includes a memory cell array, signal lines, a mode selector circuit, a command converter circuit, and an internal processor. The memory cell array includes first and second memory regions. The mode selector circuit is configured to generate a processing mode selection signal for controlling the memory device to enter an internal processing mode based on the address received together with the command. The command converter circuit is configured to convert the received command into an internal processing operation command in response to activation of the internal processing mode selection signal. The internal processor is configured to perform an internal processing operation on the first memory region in response to the internal processing operation command, in the internal processing mode.
-
公开(公告)号：US20200293452A1
公开(公告)日：2020-09-17
申请号：US16814236
申请日：2020-03-10
发明人： SUKHAN LEE , SHINHAENG KANG , NAMSUNG KIM
IPC分类号： G06F12/0875 , G06N3/08 , G06F9/30
摘要： A memory device includes a memory bank including one or more bank arrays, a PIM circuit configured to perform an operation logic processing operation, and an instruction memory including first to mth instruction queue segments configured in a circular instruction queue to store instructions provided by a host, where instructions stored in the first to mth instruction queue segments are executed in response to an operation request from the host and each new instruction provided by the host is updated over a completely executed instruction in the circular instruction queue.
-
公开(公告)号：US20240248850A1
公开(公告)日：2024-07-25
申请号：US18416558
申请日：2024-01-18
发明人： DAEHYUN KIM , SEONGMUK KANG , JIHO KIM , KYOMIN SOHN , YEONGGEOL SONG , KIJUN LEE , MYUNGKYU LEE , SUKHAN LEE
IPC分类号： G06F12/0891 , G06F12/126
CPC分类号： G06F12/0891 , G06F12/126
摘要： A memory system includes a system controller and a memory device. The system controller includes a memory controller configured to transmit a received address to a decoding module, and output, to the host device, decoded data. The decoding module includes a cache device and a decoder. The decoding module is configured to receive the data corresponding to the address from the memory device. The decoding module is configured transmit the data stored in the cache device to the memory controller in response to determining that the data corresponding to the address is stored in the cache device. The decoding module is configured to decode the data corresponding to the address to generate decoded data and store the decoded result in the cache device in response to determining that the data corresponding to the address is not stored in the cache device.
-
6.发明公开公开(公告)号：US20230236836A1
公开(公告)日：2023-07-27
申请号：US18194174
申请日：2023-03-31
发明人： SUKHAN LEE , SHINHAENG KANG , NAMSUNG KIM , SEONGIL O , HAK-SOO YU
CPC分类号： G06F9/30145 , G06F9/321 , G06F15/7821
摘要： A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.
-
-
-
-
-
搜索结果
6 条记录 (耗时 0.014 秒)
