公开(公告)号：US20230223060A1

公开(公告)日：2023-07-13

申请号：US17939016

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BAEK JIN LIM ,  YOUNGCHUL CHO ,  SEUNGJIN PARK ,  DOOBOCK LEE ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.