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    INJECTION LOCKING OSCILLATOR CIRCUIT AND OPERATING METHOD
    4.
    发明申请
    INJECTION LOCKING OSCILLATOR CIRCUIT AND OPERATING METHOD 有权

    公开(公告)号：US20220069812A1

    公开(公告)日：2022-03-03

    申请号：US17224577

    申请日：2021-04-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： YOUNG CHOI ,  WONJOO JUNG ,  YOUNGCHUL CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

    IPC: H03K5/01

    Abstract: An injection locking oscillator (ILO) circuit includes; an injection circuit that receives input signals having a phase difference and provides injection signals respectively corresponding to the input signals based on a voltage level difference between each input signal and an oscillation signal at an output terminal, and a poly-phase signal output circuit that provides poly-phased signals having a phase difference between signals fixed to a defined phase difference upon receiving the injection signals from the input terminals.

    CLOCK CONVERTING CIRCUIT WITH SYMMETRIC STRUCTURE
    5.
    发明申请
    CLOCK CONVERTING CIRCUIT WITH SYMMETRIC STRUCTURE 有权

    公开(公告)号：US20210405683A1

    公开(公告)日：2021-12-30

    申请号：US17145211

    申请日：2021-01-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Junyoung PARK ,  YOUNG-HOON SON ,  HYUN-YOON CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

    IPC: G06F1/06 ,  G06F13/40 ,  G11C11/403 ,  G11C11/406

    Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

    POWER GATING CIRCUIT AND A SEMICONDUCTOR CHIP INCLUDING THE SAME
    6.
    发明公开
    POWER GATING CIRCUIT AND A SEMICONDUCTOR CHIP INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240195406A1

    公开(公告)日：2024-06-13

    申请号：US18515355

    申请日：2023-11-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JINOOK JUNG ,  JAEWOO PARK ,  MYOUNGBO KWAK ,  JUNGHWAN CHOI

    IPC: H03K17/30 ,  H03K17/687 ,  H03K19/0185

    CPC classification number: H03K17/302 ,  H03K17/687 ,  H03K19/018507 ,  H03K2217/0081

    Abstract: A power gating circuit including: a power gating transistor; a gate bias generating circuit configured to provide a gate bias control signal to the gate of the power gating transistor; and a body bias generating circuit configured to provide a body bias control signal to the body of the power gating transistor, wherein when the power gating transistor is turned on, the gate bias generating circuit provides the gate bias control signal having a positive voltage level and the body bias generating circuit provides the body bias control signal having the positive voltage level, and when the power gating transistor is turned off, the gate bias generating circuit provides the gate bias control signal having a ground voltage level or a negative voltage level, and the body bias generating circuit provides the body bias control signal having the ground voltage level or the negative voltage level.

    SEMICONDUCTOR MEMORY MODULE INCLUDING NONVOLATILE MEMORY DEVICES
    8.
    发明申请
    SEMICONDUCTOR MEMORY MODULE INCLUDING NONVOLATILE MEMORY DEVICES 审中-公开

    公开(公告)号：US20200042232A1

    公开(公告)日：2020-02-06

    申请号：US16390077

    申请日：2019-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： TAESUNG LEE ,  JUNGHWAN CHOI

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/0866

    Abstract: A semiconductor memory module includes data buffers that exchange first data signals with an external device, nonvolatile memory devices that are respectively connected to the data buffers through data lines, and a controller connected to the data lines. The controller receives an address, a command, and a control signal from the external device, and depending on the address, the command, and the control signal, the controller controls the data buffers through first control lines and controls the nonvolatile memory devices through second control lines.

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