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公开(公告)号:US20170162668A1
公开(公告)日:2017-06-08
申请号:US15348040
申请日:2016-11-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SUNG MIN KIM , HEON JONG SHIN
IPC: H01L29/66 , H01L29/78 , H01L29/06 , H01L21/762
CPC classification number: H01L29/66545 , H01L21/28114 , H01L21/76224 , H01L29/0653 , H01L29/66795 , H01L29/785 , H01L29/7851
Abstract: A method of manufacturing a semiconductor device includes forming a fin extending in a first direction. A dummy layer is formed including a plurality of semiconductor layers disposed on the fin. Each of the plurality of semiconductor layers have different impurity concentrations from each other. The dummy layer is etched to form a dummy gate electrode.
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公开(公告)号:US20200294995A1
公开(公告)日:2020-09-17
申请号:US16734786
申请日:2020-01-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: SUNG MIN KIM , Dae Won HA
IPC: H01L27/06 , H01L27/088 , H01L23/528 , H01L29/78 , H01L29/417
Abstract: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.
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公开(公告)号:US20190139955A1
公开(公告)日:2019-05-09
申请号:US15971483
申请日:2018-05-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: SUNG MIN KIM , Dong Won KIM
IPC: H01L27/088 , H01L29/417 , H01L29/06 , H01L23/528 , H01L27/02 , H01L29/08 , H01L21/8234 , H01L29/66
Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate in a direction perpendicular to an upper surface of the substrate, the fin structure including first fin regions extending in a first direction and second fin regions extending in a second direction different from the first direction, source/drain regions disposed on the fin structure, a gate structure intersecting the fin structure, a first contact connected to one of the source/drain regions, and a second contact connected to the gate structure and being between the second fin regions in plan view.
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公开(公告)号:US20180261668A1
公开(公告)日:2018-09-13
申请号:US15726535
申请日:2017-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: JUNG GIL YANG , SEUNG MIN SONG , SUNG MIN KIM , WOO SEOK PARK , GEUM JONG BAE , DONG IL BAE
IPC: H01L29/06 , H01L29/49 , H01L29/66 , H01L29/786
CPC classification number: H01L29/0673 , H01L29/495 , H01L29/4966 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66742 , H01L29/78645
Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.
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