公开(公告)号：US20180158773A1

公开(公告)日：2018-06-07

申请号：US15638552

申请日：2017-06-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： AUGUSTIN JINWOO HONG ,  DAE-IK KIM ,  CHAN-SIC YOON ,  Kl-SEOK LEE ,  DONG-MIN HAN ,  SUNG-HO JANG ,  YOO-SANG HWANG ,  BONG-SOO KIM ,  JE-MIN PARK

IPC: H01L23/522 ,  H01L27/11568 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L27/10814 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/11568

Abstract: A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.

公开(公告)号：US20160163708A1

公开(公告)日：2016-06-09

申请号：US14957169

申请日：2015-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNG-HO JANG ,  SATORU YAMADA ,  JUN-HEE LIM ,  JU-YEON JANG ,  KYOUNG-HO JUNG ,  JOON HAN

IPC: H01L27/108 ,  G11C11/408 ,  G11C11/4091 ,  H01L27/02 ,  H01L27/092

CPC classification number: G11C11/4087 ,  G11C11/4085 ,  G11C11/4091 ,  H01L21/823462 ,  H01L21/823807 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/10894 ,  H01L27/10897

Abstract: A semiconductor device includes a semiconductor substrate having a first transistor region and a second transistor region, a first MOSFET including a first gate insulating layer structure and a first gate electrode structure, and a second MOSFET including a group IV compound semiconductor layer, a second gate insulating layer structure, and a second gate electrode structure. The first gate insulating layer structure and the first gate electrode structure are disposed on the first transistor region of the semiconductor substrate. The group IV compound semiconductor layer is disposed on the second transistor region of the semiconductor substrate, and the second gate insulating layer and the second gate electrode structure are disposed on the group IV compound semiconductor layer. Each of the first and second gate insulating layer structures includes a high-k dielectric (insulating) layer.

Abstract translation: 半导体器件包括具有第一晶体管区域和第二晶体管区域的半导体衬底，包括第一栅极绝缘层结构和第一栅极电极结构的第一MOSFET以及包括IV族化合物半导体层的第二MOSFET，第二栅极 绝缘层结构和第二栅电极结构。 第一栅极绝缘层结构和第一栅电极结构设置在半导体衬底的第一晶体管区域上。 IV族化合物半导体层设置在半导体衬底的第二晶体管区域上，第二栅极绝缘层和第二栅电极结构设置在IV族化合物半导体层上。 第一和第二栅极绝缘层结构中的每一个包括高k电介质（绝缘）层。