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公开(公告)号：US20210143154A1
公开(公告)日：2021-05-13
申请号：US17126195
申请日：2020-12-18
发明人： KISEOK LEE , BONG-SOO KIM , JIYOUNG KIM , HUI-JUNG KIM , SEOKHAN PARK , HUNKOOK LEE , YOOSANG HWANG
IPC分类号： H01L27/108 , H01L23/528 , H01L29/08 , H01L29/165 , H01L29/10
摘要： Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
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2.发明申请公开(公告)号：US20170186613A1
公开(公告)日：2017-06-29
申请号：US15291780
申请日：2016-10-12
发明人： DAE-IK KIM , EUN-JUNG KIM , YOO-SANG HWANG , BONG-SOO KIM , JE-MIN PARK
IPC分类号： H01L21/033 , H01L21/768 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/0332 , H01L21/0338 , H01L21/3086 , H01L21/31144 , H01L21/32139 , H01L21/76816
摘要： A method of forming a pattern includes forming a first level pattern layer on a feature layer on a substrate. The first level pattern layer includes a plurality of first line patterns and a plurality of first space burying patterns. The first line patterns extend parallel to one another in a first direction and the first space burying patterns extend parallel to one another in the first direction with first line patterns alternately disposed with first space burying patterns A portion of the plurality of first space burying patterns may be removed to form a second direction pattern space extending intermittently or continuously in the first level pattern layer. A second burying layer filling the second direction pattern space may be formed to form a network structure pattern. The feature layer may be etched with the network structure pattern as an etch mask to form a pattern of holes.
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公开(公告)号：US20190096890A1
公开(公告)日：2019-03-28
申请号：US15945401
申请日：2018-04-04
发明人： MYEONG-DONG LEE , JUN-WON LEE , KI SEOK LEE , BONG-SOO KIM , SEOK HAN PARK , SUNG HEE HAN , YOO SANG HWANG
IPC分类号： H01L27/108 , H01L23/532 , H01L23/522
摘要： A semiconductor device includes a substrate having a trench, a bit line in the trench, a first spacer extending along the trench and at least a portion of a side surface of the bit line and in contact with the bit line, and a second spacer disposed within the trench on the first spacer. The bit line is narrower than the trench, and the first spacer includes silicon oxide. A method of forming a semiconductor device includes forming a trench in a substrate, forming a bit line within the first trench of width less than that of the first trench, and forming a first spacer that lines a portion of the trench and includes silicon oxide in contact with at least a portion of a side surface of the bit line, and forming a second spacer over the first spacer in the trench.
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公开(公告)号：US20180122811A1
公开(公告)日：2018-05-03
申请号：US15614077
申请日：2017-06-05
发明人： DAEIK KIM , KISEOK LEE , KEUNNAM KIM , BONG-SOO KIM , JEMIN PARK , CHAN-SIC YOON , YOOSANG HWANG
IPC分类号： H01L27/108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894
摘要： Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.
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公开(公告)号：US20190325960A1
公开(公告)日：2019-10-24
申请号：US16458594
申请日：2019-07-01
发明人： SUNGWOO KIM , BONG-SOO KIM , YOUNGBAE KIM , KIJAE HUR , GWANHYEOB KOH , HYEONGSUN HONG , YOOSANG HWANG
摘要： A semiconductor device includes: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed on a substrate; and a second memory section and a wiring section that are stacked on the second peripheral circuit section, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, and the wiring section includes a plurality of line patterns, wherein the line patterns and the second memory cells are higher than the capacitor with respect to the substrate.
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公开(公告)号：US20190252386A1
公开(公告)日：2019-08-15
申请号：US16268748
申请日：2019-02-06
发明人： KISEOK LEE , BONG-SOO KIM , JIYOUNG KIM , HUI-JUNG KIM , SEOKHAN PARK , HUNKOOK LEE , YOOSANG HWANG
IPC分类号： H01L27/108 , H01L23/528 , H01L29/08 , H01L29/10 , H01L29/165
CPC分类号： H01L27/10805 , H01L23/5226 , H01L23/528 , H01L27/10897 , H01L28/60 , H01L29/0847 , H01L29/1037 , H01L29/165
摘要： Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.
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公开(公告)号：US20210125998A1
公开(公告)日：2021-04-29
申请号：US16990305
申请日：2020-08-11
发明人： SEOK-HYUN KIM , Joon Young KANG , YOUNGJUN KIM , JINHYUNG PARK , HO-JU SONG , SANG-JUN LEE , HYERAN LEE , BONG-SOO KIM , SUNGWOO KIM
IPC分类号： H01L27/108
摘要： A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.
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公开(公告)号：US20190325930A1
公开(公告)日：2019-10-24
申请号：US16460284
申请日：2019-07-02
发明人： SUNGWOO KIM , BONG-SOO KIM , YOUNGBAE KIM , KIJAE HUR , GWANHYEOB KOH , HYEONGSUN HONG , YOOSANG HWANG
IPC分类号： G11C11/00 , G11C5/02 , G11C14/00 , H01L27/108 , H01L23/528 , H01L27/24 , H01L49/02 , H01L45/00
摘要： A semiconductor device including: a first memory section, a first peripheral circuit section, and a second peripheral circuit section that are disposed next to each other on a substrate; and a second memory section laterally spaced apart from the first memory section, the second peripheral circuit section and the second memory section disposed next to each other on the substrate, wherein the first memory section includes a plurality of first memory cells, each of the first memory cells including a cell transistor and a capacitor connected to the cell transistor, and the second memory section includes a plurality of second memory cells, each of the second memory cells including a variable resistance element and a select element coupled in series to each other, wherein the second memory cells are higher from the substrate than each of the capacitors.
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公开(公告)号：US20180158773A1
公开(公告)日：2018-06-07
申请号：US15638552
申请日：2017-06-30
发明人： AUGUSTIN JINWOO HONG , DAE-IK KIM , CHAN-SIC YOON , Kl-SEOK LEE , DONG-MIN HAN , SUNG-HO JANG , YOO-SANG HWANG , BONG-SOO KIM , JE-MIN PARK
IPC分类号： H01L23/522 , H01L27/11568 , H01L21/768
CPC分类号： H01L23/5226 , H01L21/76802 , H01L27/10814 , H01L27/10888 , H01L27/10894 , H01L27/11568
摘要： A semiconductor device includes a substrate including a cell array region including a cell active region. An insulating pattern is on the substrate. The insulating pattern includes a direct contact hole which exposes the cell active region and extends into the cell active region. A direct contact conductive pattern is in the direct contact hole and is connected to the cell active region. A bit line is on the insulating pattern. The bit line is connected to the direct contact conductive pattern and extends in a direction orthogonal to an upper surface of the insulating pattern. The insulating pattern includes a first insulating pattern including a non-metal-based dielectric material and a second insulating pattern on the first insulating pattern. The second insulating pattern includes a metal-based dielectric material having a higher dielectric constant than a dielectric constant of the first insulating pattern.
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