公开(公告)号：US20220138049A1

公开(公告)日：2022-05-05

申请号：US17345276

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MI JIN LEE ,  DONG-YOON KIM ,  MIN-HYOUK KIM ,  SUNG-JOON KIM ,  SUNG UP MOON ,  JONG YOUNG LEE

IPC: G06F11/14 ,  G06F11/10 ,  G06F11/07

Abstract: A memory module includes; dynamic random access memories (DRAMs), a controller configured to control operation of the DRAMs, and an active device configured, in response to detection of an error occurring in at least one of the DRAMs, to generate an interrupt and store error information corresponding to the error.

公开(公告)号：US20230113615A1

公开(公告)日：2023-04-13

申请号：US17895227

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  SUNG-JOON KIM ,  HEEDONG KIM ,  MINSU BAE ,  ILWOONG SEO ,  MIJIN LEE ,  SEUNG JU LEE ,  HYAN SUK LEE ,  INSU CHOI ,  KIDEOK HAN

IPC: H03M13/19 ,  G11C11/408 ,  G11C11/4096 ,  H03M13/00

Abstract: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US20180039588A1

公开(公告)日：2018-02-08

申请号：US15659182

申请日：2017-07-25

Applicant: SAMSUNG ELECTRONICS CO ., LTD.

Inventor： CHANGHO YUN ,  SUNG-JOON KIM

IPC: G06F13/16

CPC classification number: G06F13/1689 ,  G11C11/406

Abstract: A memory system includes a first dual in-line memory module (DIMM), a second DIMM, and a controller. The first DIMM may include a first memory device including a first on-die termination (ODT) circuit connected to a data line. The second DIMM may include a second memory device including a second ODT circuit connected to the data line. The controller is connected to the first and second memory devices through the data line, generates first and second delay information, and determines whether to change an ODT duration of the first or second ODT circuit using the first and second delay information. The first delay information is indicative of a time taken for command/address or clock signals to reach the first memory device. The second delay information is indicative of a time taken for command/address signal or clock signals to reach the second memory device.