公开(公告)号：US20230350809A1

公开(公告)日：2023-11-02

申请号：US18140974

申请日：2023-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHINAM KIM ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DOHAN KIM ,  BYEONGNOH KIM ,  BOBAE KIM ,  CHANGMIN LEE ,  KYEONGJIN CHO ,  INSU CHOI

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: A memory device includes; a memory cell array, and a command/address decoder including a buffer memory, a first decoding logic circuit configured to decrypt command/address information, and a second decoding logic circuit configured to decrypt an address table. The command/address decoder is configured to decrypt a first command received from a memory controller through the first decoding logic circuit to obtain a table synchronization command, decrypt data received from the memory controller after a predefined latency from receipt of the first command through the second decoding logic circuit to obtain an address table, store the address table in the buffer memory, decrypt a second command received from the memory controller through the first decoding logic circuit to obtain a table-based command and index information associated with the address table, and execute the table-based command with respect to an address corresponding to the index information.

公开(公告)号：US20230113615A1

公开(公告)日：2023-04-13

申请号：US17895227

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  SUNG-JOON KIM ,  HEEDONG KIM ,  MINSU BAE ,  ILWOONG SEO ,  MIJIN LEE ,  SEUNG JU LEE ,  HYAN SUK LEE ,  INSU CHOI ,  KIDEOK HAN

IPC: H03M13/19 ,  G11C11/408 ,  G11C11/4096 ,  H03M13/00

Abstract: A memory system includes a memory module that includes a first memory device through a fourth memory device and a first error correction code (ECC) device, and a memory controller that exchanges first user data with each of the first memory device through the fourth memory device through 8 data lines and exchanges first ECC data with the first ECC device through 4 data lines. The memory controller includes an ECC engine that corrects a 32-random bit error of the first user data, based on the first ECC data.

公开(公告)号：US20210373995A1

公开(公告)日：2021-12-02

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  MINSU KIM ,  DEOKHO SEO ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G06F11/30 ,  G06F11/16

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

公开(公告)号：US20230137339A1

公开(公告)日：2023-05-04

申请号：US17932734

申请日：2022-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHO SEO ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  HOYOUNG LEE ,  INSU CHOI

IPC: H03M13/11 ,  G06F3/06 ,  H03M13/00

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US20220366949A1

公开(公告)日：2022-11-17

申请号：US17535861

申请日：2021-11-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WONJAE SHIN ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  DEOKHO SEO ,  INSU CHOI

IPC: G11C7/22 ,  G11C8/18 ,  G11C7/10

Abstract: An operation method of a memory device, having a plurality of memory cells, includes receiving a partial write command, which includes a partial write enable signal (PWE) and a plurality of mask signals, during a command/address input interval. A data strobe signal is received through a data strobe line after receiving the partial write command Data is received through a plurality of data lines in synchronization with the data strobe signal during a data input interval. A part of the data is stored in the plurality of memory cells based on the plurality of mask signals, in response to the partial write enable signal, during a data write interval.

公开(公告)号：US20250060913A1

公开(公告)日：2025-02-20

申请号：US18938050

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHO SEO ,  TAEKYEONG KO ,  NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  HOYOUNG LEE ,  INSU CHOI

IPC: G06F3/06 ,  H03M13/00 ,  H03M13/11

Abstract: A memory device includes a memory cell array including a normal region in which first data is stored and a parity region in which a parity bit for the data is stored, and an error correction code (ECC) engine. The ECC engine is configured to determine whether there is an error in the first data based on the first data and the parity bit, and to output, in response to receiving an uncorrected read command from a memory controller, second data in a state in which an error bit in the first data is not corrected.

公开(公告)号：US20240038319A1

公开(公告)日：2024-02-01

申请号：US18222563

申请日：2023-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： NAMHYUNG KIM ,  DAEJEONG KIM ,  DOHAN KIM ,  DEOKHO SEO ,  JAEIN SONG ,  INSU CHOI

IPC: G11C29/44 ,  G11C29/12 ,  G11C29/02

CPC classification number: G11C29/44 ,  G11C29/1201 ,  G11C29/027

Abstract: A memory system including a memory device that receives a plurality of signals including a post package repair (PPR) command from a host, wherein the memory device includes a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a plurality of redundancy memory cells connected to one or more redundancy word lines and the plurality of bit lines, and anti-fuse memory cells, and a PPR control circuit that transmits to the host whether a PPR operation on a defective memory cell of the memory cell array has passed.

公开(公告)号：US20220139485A1

公开(公告)日：2022-05-05

申请号：US17388238

申请日：2021-07-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAEJEONG KIM ,  NAMHYUNG KIM ,  DOHAN KIM ,  DEOKHO SEO ,  WONJAE SHIN ,  INSU CHOI

IPC: G11C29/42 ,  G06F11/10 ,  G11C29/50

Abstract: A memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into multiple regions. The test controller is configured to perform a parallel bit test (PBT) on the plurality of memory cells, where the test controller selects fail data including a fail data bit among internal data output from the multiple regions during the PBT, and outputs the fail data via a data input/output signal line to the outside of the memory device.

公开(公告)号：US20210374001A1

公开(公告)日：2021-12-02

申请号：US17108331

申请日：2020-12-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  NAM HYUNG KIM ,  DAE-JEONG KIM ,  DO-HAN KIM ,  DEOKHO SEO ,  WONJAE SHIN ,  YONGJUN YU ,  CHANGMIN LEE ,  INSU CHOI

IPC: G06F11/10 ,  G11C11/408 ,  G11C11/4091

Abstract: A memory device includes a peripheral circuit communicating with memory banks. Each of the banks includes a memory cell array including memory cells, a row decoder connected with the memory cells through word lines, bit line sense amplifiers connected with the memory cells through bit lines including first bit lines and second bit lines, and a column decoder configured to connect the bit line sense amplifiers with the peripheral circuit. The memory cell array includes a first section connected with the first bit lines and a second section connected with the second bit lines, and the first section and second section are independent of each other with regard to a row-dependent error.

公开(公告)号：US20190303226A1

公开(公告)日：2019-10-03

申请号：US16218720

申请日：2018-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINSU KIM ,  JISEOK KANG ,  MINSOO KIM ,  BYUNGJIK KIM ,  WONJAE SHIN ,  DONGHOON LEE ,  YEONHWA LEE ,  HO-YOUNG LEE ,  YOUJIN JANG ,  INSU CHOI

IPC: G06F11/07 ,  G06F12/0804 ,  G06F12/02

Abstract: A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.