公开(公告)号：US12142650B2

公开(公告)日：2024-11-12

申请号：US18495292

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.

公开(公告)号：US20240063275A1

公开(公告)日：2024-02-22

申请号：US18495292

申请日：2023-10-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/41733 ,  H01L29/66742 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6684 ,  H01L27/088

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.

公开(公告)号：US11837638B2

公开(公告)日：2023-12-05

申请号：US17335413

申请日：2021-06-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang Hoon Lee ,  Chang Woo Sohn ,  Keun Hwi Cho ,  Sang Won Baek

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/285 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/41733 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/6684 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78391 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes first and second isolation regions, a first active region extending in a first direction between the first and second isolation regions, a first fin pattern on the first active region, nanowires on the first fin pattern, a gate electrode in a second direction on the first fin pattern, the gate electrode surrounding the nanowires, a first source/drain region on a side of the gate electrode, the first source/drain region being on the first active region and in contact with the nanowires, and a first source/drain contact on the first source/drain region, the first source/drain contact including a first portion on a top surface of the first source/drain region, and a second portion extending toward the first active region along a sidewall of the first source/drain region, an end of the first source/drain contact being on one of the first and second isolation regions.