Image sensor device and operation method thereof

    公开(公告)号:US12096148B2

    公开(公告)日:2024-09-17

    申请号:US17970986

    申请日:2022-10-21

    IPC分类号: H04N25/772 H04N25/709

    CPC分类号: H04N25/772 H04N25/709

    摘要: An image sensor device includes a first image pixel connected to a first data line, a second image pixel connected to the first data line, an analog-to-digital converter that generates a digital signal based on a ramp signal and a voltage level of the first data line, and a clamp signal generator that generates a clamp signal depending on an analog gain of the analog-to-digital converter. While a data voltage is provided from the first image pixel to the first data line, the second image pixel provides a clamp voltage to the first data line based on the clamp signal.

    SEMICONDUCTOR DEVICES HAVING IMAGE SENSOR AND MEMORY DEVICE OPERATION MODES
    2.
    发明申请
    SEMICONDUCTOR DEVICES HAVING IMAGE SENSOR AND MEMORY DEVICE OPERATION MODES 有权
    具有图像传感器和存储器件操作模式的半导体器件

    公开(公告)号:US20140104263A1

    公开(公告)日:2014-04-17

    申请号:US14050993

    申请日:2013-10-10

    IPC分类号: G09G3/36

    摘要: A semiconductor device may include a plurality of banks; and a control unit configured to receive a command from an external device and independently control the plurality of banks according to the received command. Each bank comprises a pixel array including a plurality of pixels; a row decoder configured to activate word lines connected to the plurality of pixels under control of the control unit; a column decoder configured to activate bit lines connected to the plurality of pixels under control of the control unit; a sense amplifier and write driver configured to control and detect respective voltages of the activated bit lines to provide respective amplified voltages; and an input/output buffer configured to output data states of the pixels based on the respective amplified voltages. Related methods of operation are also discussed.

    摘要翻译: 半导体器件可以包括多个堤; 以及控制单元,被配置为从外部设备接收命令,并根据所接收的命令独立地控制所述多个存储体。 每个存储体包括包括多个像素的像素阵列; 行解码器,被配置为在所述控制单元的控制下激活连接到所述多个像素的字线; 列解码器,被配置为在所述控制单元的控制下激活连接到所述多个像素的位线; 读出放大器和写入驱动器,被配置为控制和检测激活的位线的相应电压以提供相应的放大电压; 以及输入/输出缓冲器,被配置为基于相应的放大电压输出像素的数据状态。 还讨论了相关的操作方法。

    Image sensor device and operation method thereof

    公开(公告)号:US12058465B2

    公开(公告)日:2024-08-06

    申请号:US17970986

    申请日:2022-10-21

    IPC分类号: H04N25/772 H04N25/709

    CPC分类号: H04N25/772 H04N25/709

    摘要: An image sensor device includes a first image pixel connected to a first data line, a second image pixel connected to the first data line, an analog-to-digital converter that generates a digital signal based on a ramp signal and a voltage level of the first data line, and a clamp signal generator that generates a clamp signal depending on an analog gain of the analog-to-digital converter. While a data voltage is provided from the first image pixel to the first data line, the second image pixel provides a clamp voltage to the first data line based on the clamp signal.

    Image sensor and operation method of the image sensor

    公开(公告)号:US11800250B2

    公开(公告)日:2023-10-24

    申请号:US17978568

    申请日:2022-11-01

    摘要: Provided is an image sensor and an operation method of the image sensor. The image sensor includes a pixel array including a plurality of white pixels, a plurality of color pixels, and a plurality of auto focus (AF) pixels, a first shared pixel including the plurality of white pixels and the plurality of color pixels includes a first conversion gain transistor and a second conversion gain transistor configured to control a conversion gain of the first shared pixel, and a second shared pixel including some of the plurality of white pixels and the plurality of color pixels and at least one AF pixel includes a third conversion gain transistor and a fourth conversion gain transistor configured to control a conversion gain of the second shared pixel. The first conversion gain transistor, the second conversion gain transistor, the third conversion gain transistor, and the fourth conversion gain transistor are connected to different conversion gain control lines, respectively.

    Image sensor
    5.
    发明授权

    公开(公告)号:US11363231B2

    公开(公告)日:2022-06-14

    申请号:US17333712

    申请日:2021-05-28

    IPC分类号: H04N5/378 H04N5/369 H04N5/376

    摘要: An image sensor includes a pixel array including a plurality of pixels connected to row lines extending in a first direction and to column lines extending in a second direction intersecting the first direction, a ramp voltage generator configured to output a ramp voltage, a plurality of comparators, each of the plurality of comparators including a first input terminal to which the ramp voltage is input, and a second input terminal connected to one of the column lines, and a replica circuit having a same structure as a structure of a portion of the comparators. Each of the comparators includes a plurality of transistors, a first auto-zero transistor connected to the first input terminal, a second auto-zero transistor connected to the second input terminal, and wirings connected to the plurality of transistors, the first auto-zero transistor, and the second auto-zero transistor.

    Semiconductor devices having image sensor and memory device operation modes
    6.
    发明授权
    Semiconductor devices having image sensor and memory device operation modes 有权
    具有图像传感器和存储器件操作模式的半导体器件

    公开(公告)号:US09082368B2

    公开(公告)日:2015-07-14

    申请号:US14050993

    申请日:2013-10-10

    摘要: A semiconductor device may include a plurality of banks; and a control unit configured to receive a command from an external device and independently control the plurality of banks according to the received command. Each bank comprises a pixel array including a plurality of pixels; a row decoder configured to activate word lines connected to the plurality of pixels under control of the control unit; a column decoder configured to activate bit lines connected to the plurality of pixels under control of the control unit; a sense amplifier and write driver configured to control and detect respective voltages of the activated bit lines to provide respective amplified voltages; and an input/output buffer configured to output data states of the pixels based on the respective amplified voltages. Related methods of operation are also discussed.

    摘要翻译: 半导体器件可以包括多个堤; 以及控制单元,被配置为从外部设备接收命令,并根据所接收的命令独立地控制所述多个存储体。 每个存储体包括包括多个像素的像素阵列; 行解码器,被配置为在所述控制单元的控制下激活连接到所述多个像素的字线; 列解码器,被配置为在所述控制单元的控制下激活连接到所述多个像素的位线; 读出放大器和写入驱动器,被配置为控制和检测激活的位线的相应电压以提供相应的放大电压; 以及输入/输出缓冲器,被配置为基于相应的放大电压输出像素的数据状态。 还讨论了相关的操作方法。