公开(公告)号：US10163475B2

公开(公告)日：2018-12-25

申请号：US15647658

申请日：2017-07-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang-Yeon Yu ,  June-Hong Park ,  Seong-Jin Kim

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/12 ,  G11C7/14 ,  G11C7/18 ,  G11C8/14 ,  G11C29/02 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32

Abstract: A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period.

公开(公告)号：US10170192B2

公开(公告)日：2019-01-01

申请号：US15717992

申请日：2017-09-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.

公开(公告)号：US09450720B2

公开(公告)日：2016-09-20

申请号：US14304198

申请日：2014-06-13

Applicant: Samsung Electronics Co., Ltd. ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Jeong-Ho Park ,  Yong Hoon Lee ,  Min-Hyun Kim ,  Seong-Jin Kim ,  Hyun-Jeong Kang

IPC: H04W72/04 ,  H04L5/00 ,  H04B7/04 ,  H04B7/26 ,  H04B7/08

CPC classification number: H04L5/0037 ,  H04B7/086 ,  H04B7/2643 ,  H04L5/0023 ,  H04W72/046

Abstract: A method and apparatus for operating an analog beam is provided. The apparatus includes a hybrid beam-forming structure having a small number of digital chains provided in a digital stage and a signal is transmitted and received in a Time Division Multiple Access (TDMA) scheme. The apparatus includes an analog beam-forming operating unit configured to change the analog beam for a counterpart device for which use of a next frame is to be permitted, upon receiving a request for using the next frame from at least one of multiple devices that transmit and receive signals in units of frames and a communication unit configured to transmit information indicating that the analog beam is changed to permit the use of the next frame by the counterpart device to the multiple devices.

Abstract translation: 提供了一种用于操作模拟光束的方法和装置。 该装置包括具有在数字级中提供的少量数字链的混合波束形成结构，并且以时分多址（TDMA）方案发送和接收信号。 该装置包括：模拟波束形成操作单元，被配置为在从发送的多个设备中的至少一个接收到使用下一帧的请求时，改变用于下一帧的允许的对方设备的模拟波束 并以帧为单位接收信号，通信单元被配置为发送指示模拟波束被改变的信息，以允许对方设备使用下一帧到多个设备。

公开(公告)号：US10593408B2

公开(公告)日：2020-03-17

申请号：US16191656

申请日：2018-11-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： June-Hong Park ,  Ki-Whan Song ,  Bong-Soon Lim ,  Su-Chang Jeon ,  Jin-Young Kim ,  Chang-Yeon Yu ,  Dong-Kyo Shim ,  Seong-Jin Kim

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C7/10 ,  G11C16/26 ,  G11C7/12 ,  G11C16/04 ,  G11C16/32

Abstract: A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.