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公开(公告)号：US10593408B2
公开(公告)日：2020-03-17
申请号：US16191656
申请日：2018-11-15
发明人： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
摘要： A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
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公开(公告)号：US10102909B2
公开(公告)日：2018-10-16
申请号：US15484580
申请日：2017-04-11
发明人： Sang-Won Park , Su-Chang Jeon , Dong-Kyo Shim
摘要： A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
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公开(公告)号：US10395741B2
公开(公告)日：2019-08-27
申请号：US16139921
申请日：2018-09-24
发明人： Sang-Won Park , Su-Chang Jeon , Dong-Kyo Shim
摘要： A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
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公开(公告)号：US10170192B2
公开(公告)日：2019-01-01
申请号：US15717992
申请日：2017-09-28
发明人： June-Hong Park , Ki-Whan Song , Bong-Soon Lim , Su-Chang Jeon , Jin-Young Kim , Chang-Yeon Yu , Dong-Kyo Shim , Seong-Jin Kim
摘要： A nonvolatile memory device including a memory cell array having a plurality of planes; a plurality of page buffers arranged corresponding to each of the plurality of planes; and a control logic circuit configured to transmit a bit line setup signal to each of the plurality of page buffers. Each of the plurality of page buffers includes a precharge circuit configured to precharge a sensing node and a bit line in response to the bit line setup signal, and a shutoff circuit configured to perform a bit line shutoff operation in response to a bit line shutoff signal. The control logic circuit is configured to control a transition time when a level of the bit line setup signal is changed according to a gradient of the bit line shutoff signal which is changed from a first level to a second level.
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公开(公告)号：US10061538B2
公开(公告)日：2018-08-28
申请号：US15336014
申请日：2016-10-27
发明人： Sang-Soo Park , Dong-Kyo Shim
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0685 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3459 , G11C2211/5642 , G11C2211/5643 , G11C2211/5644
摘要： A memory device is provided as follows. A memory cell array includes a plurality of memory cells, and the plurality of memory cells are divided into a first memory group and a second memory group. A first page buffer group is coupled to the first memory group and includes a plurality of first page buffers. A second page buffer group is coupled to the second memory group and includes a plurality of second page buffers. The first page buffer group performs a first data processing operation on data stored in the first page buffer group and stores a result of the first data processing operation. The second page buffer group performs a second data processing operation on data stored in the second page buffer group and stores a result of the second data processing operation. The first and second data processing operations are performed at substantially the same.
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公开(公告)号：US09991007B2
公开(公告)日：2018-06-05
申请号：US15207774
申请日：2016-07-12
发明人： Ji-Sang Lee , Sang-Soo Park , Dong-Kyo Shim
IPC分类号： G11C29/12 , G11C7/10 , G11C7/12 , G11C7/14 , G11C7/22 , G11C8/10 , G11C29/56 , G11C11/56 , G11C29/42 , G11C29/52 , G11C16/04 , G11C16/26 , G11C29/50 , G11C29/04 , G11C27/02
CPC分类号： G11C29/1201 , G11C7/1006 , G11C7/1039 , G11C7/1057 , G11C7/106 , G11C7/12 , G11C7/14 , G11C7/222 , G11C8/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C27/02 , G11C29/42 , G11C29/50012 , G11C29/52 , G11C29/56008 , G11C2029/0411 , G11C2029/5004 , G11C2211/5642
摘要： A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≤N, L>1, P≤M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.
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7.发明授权Method of programming a nonvolatile memory device and nonvolatile memory device performing the method 有权执行该方法的非易失性存储器件和非易失性存储器件的编程方法公开(公告)号：US08854879B2
公开(公告)日：2014-10-07
申请号：US13755448
申请日：2013-01-31
发明人： Dong-Kyo Shim , Min-Seok Kim , Tae-Young Kim , Ki-Tae Park , Jae-Yong Jeong
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418
摘要： A method of programming a nonvolatile memory device including multi-level cells that store multi-bit data, includes performing a pre-programming operation that programs at least some of the multi-level cells to a plurality of intermediate states which are different from an erased state, and performing a main programming operation that programs the multi-level cells to a plurality of target states corresponding to the multi-bit data. At least some of the intermediate program states have threshold voltage distributions that partially overlap each other.
摘要翻译： 一种编程包括存储多位数据的多电平单元的非易失性存储器件的方法包括执行将至少一些多电平单元编程为与被擦除的多个等级单元不同的多个中间状态的预编程操作 状态，并且执行将多电平单元编程为对应于多位数据的多个目标状态的主编程操作。 至少一些中间程序状态具有部分彼此重叠的阈值电压分布。
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