公开(公告)号：US20250149508A1

公开(公告)日：2025-05-08

申请号：US18674207

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeonil Lee ,  Seryeun Yang ,  Dongkyun Lim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device includes a first chip structure that includes a memory structure and a cell routing interconnection structure that is electrically connected to the memory structure, a second chip structure that is on the first chip structure and includes a first peripheral circuit, a second peripheral circuit, a first peripheral routing interconnection structure that is electrically connected to the first peripheral circuit and the cell routing interconnection structure, and a second peripheral routing interconnection structure that is electrically connected to the second peripheral circuit, and a connection structure that extends into the first chip structure and the second chip structure, where the connection structure includes: a first connection pad, a second connection pad that overlaps the first connection pad, and an intermediate connection structure that is between the first connection pad and the second connection pad and is electrically connected to the second peripheral routing interconnection structure.

公开(公告)号：US20240357831A1

公开(公告)日：2024-10-24

申请号：US18532504

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seryeun Yang ,  Jeon Il Lee ,  Hyeran Lee ,  Hyun-Mook Choi

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

CPC classification number: H10B53/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device may include a substrate; semiconductor patterns that are stacked on the substrate, extend in a first direction parallel to a top surface of the substrate, and are spaced apart from each other; a gate electrode including horizontal portions, that extend in a second direction crossing the first direction, and a vertical portion, that is in contact with the horizontal portions and extends in a third direction perpendicular to the top surface of the substrate; a gate dielectric layer between the semiconductor patterns and the gate electrode; and a ferroelectric layer between the gate dielectric layer and the gate electrode. Each of the semiconductor patterns may include impurity regions and a channel region between the impurity regions, the vertical portion may be on a first side surface of the channel region, and the horizontal portions may be on a top and bottom surface of the channel region.

公开(公告)号：US20230369214A1

公开(公告)日：2023-11-16

申请号：US18195646

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Seryeun Yang ,  Hyeran Lee

IPC: H01L23/528

CPC classification number: H01L23/5283 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40

Abstract: A semiconductor device is provided. The semiconductor device includes: first lower conductive lines extending in a first direction and disposed at a first height level; first upper conductive lines extending in the first direction and vertically overlapping the first lower conductive lines at a second height level, higher than the first height level; single crystal semiconductor patterns disposed between the first lower conductive lines and the first upper conductive lines at a third height level; intermediate conductive lines extending in a second direction intersecting the first direction and passing between the single crystal semiconductor patterns, between the first height level and the second height level; and data storage layers including portions between the intermediate conductive lines and the single crystal semiconductor patterns.

公开(公告)号：US20250105150A1

公开(公告)日：2025-03-27

申请号：US18625407

申请日：2024-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeon Il Lee ,  Seryeun Yang ,  Dongkyun Lim

IPC: H01L23/528 ,  H01L23/522 ,  H01L25/065 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device may include a substrate that includes a first surface and a second surface opposite to each other, a first driving transistor and a second driving transistor on the first surface of the substrate, a first insulation layer on the first surface of the substrate, a second insulation layer on the second surface of the substrate, a first penetration electrode and a second penetration electrode that extend into the substrate, the first insulation layer, and the second insulation layer, a first contact plug extending in the first insulation layer and electrically connected to the first driving transistor and the first penetration electrode, and a second contact plug extending in the substrate and the second insulation layer and electrically connected to the second driving transistor and the second penetration electrode.

公开(公告)号：US20230157036A1

公开(公告)日：2023-05-18

申请号：US17839612

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seryeun Yang

IPC: H01L27/105

CPC classification number: H01L27/1052

Abstract: A semiconductor memory device may include a substrate including an active pattern, the active pattern including first and second source/drain regions spaced apart from each other, a bit line that is electrically connected to the first source/drain region and crosses the active pattern, a storage node contact electrically connected to the second source/drain region, a spacer structure between the bit line and the storage node contact, a landing pad electrically connected to the storage node contact, an insulating pattern on the spacer structure and adjacent to the landing pad, and a liner between the insulating pattern and the landing pad. The insulating pattern may include an upper insulating portion and a lower insulating portion between the upper insulating portion and the spacer structure. The largest width of the lower insulating portion may be larger than the smallest width of the upper insulating portion.