公开(公告)号：US11801602B2

公开(公告)日：2023-10-31

申请号：US17420859

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyong Ju ,  Hyeran Lee ,  Hyunjung Nam ,  Miyoung Kim ,  Jaebum Park ,  Joonah Park

IPC: B25J9/16 ,  B25J19/02 ,  G05D1/02 ,  B25J11/00

CPC classification number: B25J9/1664 ,  B25J9/1697 ,  B25J11/0005 ,  B25J19/023 ,  G05D1/0246

Abstract: Provided are a mobile robot and a method of driving the same. A method in which the mobile robot moves along with a user includes photographing surroundings of the mobile robot, detecting the user from an image captured by the photographing, tracking a location of the user within the image as the user moves, predicting a movement direction of the user, based on a last location of the user within the image, when the tracking of the location of the user is stopped, and determining a traveling path of the mobile robot, based on the predicted movement direction of the user.

公开(公告)号：US11183500B2

公开(公告)日：2021-11-23

申请号：US16826655

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoju Song ,  Seokhyun Kim ,  Youngjun Kim ,  Jinhyung Park ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

公开(公告)号：US20230413538A1

公开(公告)日：2023-12-21

申请号：US18148566

申请日：2022-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeran Lee ,  Junhyeok Ahn ,  Kiseok Lee

IPC: H10B12/00 ,  H01L29/423 ,  H01L23/528

CPC classification number: H10B12/488 ,  H01L23/5283 ,  H10B12/482 ,  H01L29/4236

Abstract: An integrated circuit device includes a substrate comprising an active region and a word line trench, a word line extending longitudinally in a first horizontal direction in the word line trench, a buried insulating layer on the word line, a conductive plug on the substrate, and a pad structure on the substrate and having a portion in contact with a top surface of the active region and a portion in contact with the conductive plug. The pad structure includes a conductive pad having a bottom surface in contact with the top surface of the active region and a pad spacer in contact with a sidewall of the conductive pad and protruding beyond an inner sidewall of the word line trench in a second horizontal direction orthogonal to the first horizontal direction such that the pad spacer vertically overlaps a portion of the word line in the word line trench.

公开(公告)号：US20220254787A1

公开(公告)日：2022-08-11

申请号：US17667697

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/108

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11251188B2

公开(公告)日：2022-02-15

申请号：US16990305

申请日：2020-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seok-Hyun Kim ,  Joon Young Kang ,  Youngjun Kim ,  Jinhyung Park ,  Ho-Ju Song ,  Sang-Jun Lee ,  Hyeran Lee ,  Bong-Soo Kim ,  Sungwoo Kim

IPC: H01L27/088 ,  H01L21/00 ,  H01L27/108

Abstract: A semiconductor memory device including: a substrate including a cell array region and a boundary region; a first recess region at an upper portion of the substrate in the cell array region; a first bit line extending onto the boundary region and crossing the first recess region; a bit line contact in the first recess region and contacting the first bit line; a second bit line spaced apart from the first recess region and adjacent to the first bit line, the second bit line crossing the cell array region and the boundary region; a cell buried insulation pattern between a side surface of the first bit line contact and an inner wall of the first recess region; and a boundary buried insulation pattern covering sidewalls of the first bit line and the second bit line in the boundary region and including a same material as the cell buried insulation pattern.

公开(公告)号：US20210035983A1

公开(公告)日：2021-02-04

申请号：US16826655

申请日：2020-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoju Song ,  Seokhyun Kim ,  Youngjun Kim ,  Jinhyung Park ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/108

Abstract: A method of manufacturing a semiconductor memory device includes forming bit line structures extending in a first horizontal direction on a substrate, and insulating spacer structures covering opposite sidewalls of each bit line structure, forming a preliminary buried contact material layer and a mold layer to respectively fill lower and upper portions of a space between a pair of insulating spacer structures, patterning the mold layer and the preliminary buried contact material layer into mold patterns spaced apart from each other in a second horizontal direction and buried contacts spaced apart from each other in the second horizontal direction, forming insulating fences among the mold patterns separated from each other and among the buried contacts separated from each other, removing the mold patterns to expose the buried contacts, and forming landing pads on the exposed buried contacts, each landing pad connected to a corresponding one of the exposed buried contacts.

公开(公告)号：US20250151260A1

公开(公告)日：2025-05-08

申请号：US18739698

申请日：2024-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyuk Kim ,  Taejin Park ,  Hyeran Lee ,  Sungsoo Yim

IPC: H10B12/00 ,  H01L29/78

Abstract: A semiconductor device includes bit line structures spaced apart from each other in a first direction, and each of the bit line structures extends in a second direction; channels on the bit line structures, wherein the channels are electrically connected to the bit line structures and spaced apart from each other in the first direction; a gate insulation pattern structure on sidewalls of each of the channels; a gate electrode structure including: a first gate electrode on a first sidewall of the gate insulation pattern structure; and a second gate electrode on a second sidewall of the gate insulation pattern structure, wherein the second sidewall faces the first sidewall in the second direction, wherein the second gate electrode is on a third sidewall in the first direction of an end portion of the gate insulation pattern structure, and wherein the second gate electrode contacts the first gate electrode.

公开(公告)号：US20240357831A1

公开(公告)日：2024-10-24

申请号：US18532504

申请日：2023-12-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seryeun Yang ,  Jeon Il Lee ,  Hyeran Lee ,  Hyun-Mook Choi

IPC: H10B53/20 ,  H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

CPC classification number: H10B53/20 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/10 ,  H10B51/20 ,  H10B53/10

Abstract: A semiconductor device may include a substrate; semiconductor patterns that are stacked on the substrate, extend in a first direction parallel to a top surface of the substrate, and are spaced apart from each other; a gate electrode including horizontal portions, that extend in a second direction crossing the first direction, and a vertical portion, that is in contact with the horizontal portions and extends in a third direction perpendicular to the top surface of the substrate; a gate dielectric layer between the semiconductor patterns and the gate electrode; and a ferroelectric layer between the gate dielectric layer and the gate electrode. Each of the semiconductor patterns may include impurity regions and a channel region between the impurity regions, the vertical portion may be on a first side surface of the channel region, and the horizontal portions may be on a top and bottom surface of the channel region.

公开(公告)号：US20240155836A1

公开(公告)日：2024-05-09

申请号：US18492821

申请日：2023-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonyoung Kang ,  Hoju Song ,  Kanguk Kim ,  Seokhyun Kim ,  Youngjun Kim ,  Jooncheol Kim ,  Jinwoong Kim ,  Hoin Ryu ,  Hyeran Lee

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/02 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: Semiconductor devices may include: a substrate including a plurality of active areas defined by a device isolation layer; a plurality of bit lines extending on the substrate in a first horizontal direction; a plurality of insulation fences that are spaced apart from each other in the first horizontal direction in a space between two adjacent bit lines among the plurality of bit lines on the substrate; a plurality of buried contacts that are between the adjacent two bit lines among the plurality of bit lines and are arranged alternately with the plurality of insulation fences along the first horizontal direction on the substrate, the plurality of buried contacts being connected to the plurality of active areas, respectively; and a plurality of insulating layer, each of which is between a respective one of the plurality of insulation fences and a respective one of the plurality of buried contacts.

公开(公告)号：US20230395567A1

公开(公告)日：2023-12-07

申请号：US18066558

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyong Um ,  Hyeran Lee

IPC: H01L25/065 ,  H01L27/146 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L27/14636 ,  H01L25/50 ,  H01L2225/06582 ,  H01L2225/06541

Abstract: A semiconductor package includes first, second, and third semiconductor chips. The second semiconductor chip includes a semiconductor substrate, a first wiring layer on a first surface of the semiconductor substrate, a second wiring layer on a second surface of the semiconductor substrate, and a through via that penetrates the semiconductor substrate and electrically connects the first wiring layer and the second wiring layer. The semiconductor substrate and the through via are spaced apart from each other across a spacer structure. The spacer structure includes a first liner layer in contact with the semiconductor substrate, a second liner layer in contact with the through via, an air gap between the first liner layer and the second liner layer, and a capping layer that seals the air gap on the first liner layer and the second liner layer.