公开(公告)号：US09882565B2

公开(公告)日：2018-01-30

申请号：US15141050

申请日：2016-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siddharth Katare ,  Jeong-Don Ihm

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.

公开(公告)号：US20170060164A1

公开(公告)日：2017-03-02

申请号：US15224927

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Don Ihm ,  Siddharth Katare

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A regulator circuit includes a power transistor, a current minor, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current minor provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.

Abstract translation: 调节器电路包括功率晶体管，电流辅助电极，第一NMOS晶体管，第二NMOS晶体管和电流源。 功率晶体管具有连接到外部电源电压源的源极，连接到具有连接到输出内部电源电压的第二节点的第一电压和漏极的第一节点的栅极。 当前小电流向具有第二电压的第三节点提供第一电流，并向第一节点提供第二电流。 第一NMOS晶体管具有连接到第一节点的漏极，接收第一参考电压的栅极和连接到第四节点的源极。 第二NMOS晶体管具有连接到第三节点的漏极，连接到第二节点的栅极和连接到第四节点的源极。

公开(公告)号：US09904310B2

公开(公告)日：2018-02-27

申请号：US15224927

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Don Ihm ,  Siddharth Katare

IPC: G05F1/44 ,  G05F3/26

CPC classification number: G05F3/262

Abstract: A regulator circuit includes a power transistor, a current mirror, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to an external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current mirror provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.