公开(公告)号：US11742040B2

公开(公告)日：2023-08-29

申请号：US17704345

申请日：2022-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C16/06 ,  G11C29/02 ,  G11C5/06 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C29/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/06 ,  G11C16/102 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US09653132B2

公开(公告)日：2017-05-16

申请号：US15051896

申请日：2016-02-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Hoon Na ,  Hyun-Jin Kim ,  Jeong-Don Ihm

IPC: G11C8/12 ,  G11C16/08 ,  H01L23/00 ,  H01L25/065 ,  G11C16/10 ,  H01L23/525 ,  G11C5/06 ,  G11C16/26 ,  G11C5/04 ,  G11C5/02

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/063 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/48 ,  G11C2029/4402 ,  H01L23/50 ,  H01L23/5256 ,  H01L24/06 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/48137 ,  H01L2224/48177 ,  H01L2225/06506 ,  H01L2924/00014 ,  H01L2924/1438 ,  H01L2224/45099

Abstract: A semiconductor package includes an external electrode, an interface chip, and a semiconductor chip. The interface chip includes an external interface pad bonded to the external electrode, a plurality of internal interface pads, and an interface circuit coupled between the external interface pad and the plurality of internal interface pads. The semiconductor chip includes a signal pad that is selectively bonded to one of the plurality of internal interface pads. The interface circuit activates a connection between a selected pad, which corresponds to a pad that is bonded to the signal pad among the plurality of internal interface pads, and the external interface pad, and deactivates connections between unselected pads, which correspond to pads that are not bonded to the signal pad among the plurality of internal interface pads, and the external interface pad.

公开(公告)号：US20170060164A1

公开(公告)日：2017-03-02

申请号：US15224927

申请日：2016-08-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Don Ihm ,  Siddharth Katare

IPC: G05F3/26

CPC classification number: G05F3/262

Abstract: A regulator circuit includes a power transistor, a current minor, a first NMOS transistor, a second NMOS transistor and a current source. The power transistor has a source connected to external power supply voltage supply, a gate connected to a first node having a first voltage and a drain connected to a second node outputting an internal power supply voltage. A current minor provides a first current to a third node having a second voltage and provides a first node with a second current. A first NMOS transistor has a drain connected to a first node, a gate receiving a first reference voltage and a source connected to a fourth node. A second NMOS transistor has a drain connected to a third node, a gate connected to a second node and a source connected to the fourth node.

Abstract translation: 调节器电路包括功率晶体管，电流辅助电极，第一NMOS晶体管，第二NMOS晶体管和电流源。 功率晶体管具有连接到外部电源电压源的源极，连接到具有连接到输出内部电源电压的第二节点的第一电压和漏极的第一节点的栅极。 当前小电流向具有第二电压的第三节点提供第一电流，并向第一节点提供第二电流。 第一NMOS晶体管具有连接到第一节点的漏极，接收第一参考电压的栅极和连接到第四节点的源极。 第二NMOS晶体管具有连接到第三节点的漏极，连接到第二节点的栅极和连接到第四节点的源极。

公开(公告)号：US09461656B2

公开(公告)日：2016-10-04

申请号：US14558072

申请日：2014-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hye-Yoon Joo ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song ,  Jeong-Don Ihm

IPC: H03L7/06 ,  H03L7/087 ,  H03L7/07 ,  H03L7/083 ,  H03L7/099 ,  G11C7/22

CPC classification number: H03L7/087 ,  G11C7/222 ,  H03L7/07 ,  H03L7/083 ,  H03L7/0995

Abstract: An injection-locked phase-locked loop (ILPLL) circuit includes a delay-locked loop (DLL) and an ILPLL. The DLL is configured to generate a DLL clock by performing a delay-locked operation on a reference clock. The ILPLL includes a voltage-controlled oscillator (VCO), and is configured to generate an output clock by performing an injection synchronous phase-locked operation on the reference clock. The DLL clock is injected into the VCO as an injection clock of the VCO.

Abstract translation: 注射锁相环（ILPLL）电路包括延迟锁定环（DLL）和ILPLL。 DLL被配置为通过对参考时钟执行延迟锁定操作来生成DLL时钟。 ILPLL包括压控振荡器（VCO），并且被配置为通过对参考时钟执行注入同步锁相操作来产生输出时钟。 将DLL时钟作为VCO的注入时钟注入到VCO中。

公开(公告)号：US11804270B2

公开(公告)日：2023-10-31

申请号：US17460954

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Yeon Shin ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Jung-June Park

IPC: G11C16/30 ,  G11C7/10 ,  G11C16/26 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/30 ,  G11C7/1051 ,  G11C16/26 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

公开(公告)号：US10937471B2

公开(公告)日：2021-03-02

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/06 ,  G11C16/26

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10741225B2

公开(公告)日：2020-08-11

申请号：US16802084

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10340022B2

公开(公告)日：2019-07-02

申请号：US15977553

申请日：2018-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: H03K19/177 ,  G11C29/02 ,  G11C7/10 ,  G11C5/06 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US09882565B2

公开(公告)日：2018-01-30

申请号：US15141050

申请日：2016-04-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Siddharth Katare ,  Jeong-Don Ihm

IPC: H03K19/0185

CPC classification number: H03K19/018521

Abstract: A buffer circuit includes first and second current generators, a comparator, a differential driver, and an inverter. The first current generator outputs a first current corresponding to a reference voltage. The second current generator generates a limit current corresponding to an input limit voltage, and outputs a second current having a size equal to about half of the limit current. The sizes of the first current and the limit current are controlled by the feedback voltage. The comparator generates the feedback voltage by comparing the first and second currents. The differential driver generates an internal current, and controls the internal current based on the feedback voltage. The magnitudes of an upper limit value and a lower limit value of the internal current are substantially equal to each other with respect to a reference value. The inverter generates an output current by inverting the internal current based on supply voltage.

公开(公告)号：US11705166B2

公开(公告)日：2023-07-18

申请号：US17182357

申请日：2021-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C2207/105

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.