公开(公告)号：US20240107763A1

公开(公告)日：2024-03-28

申请号：US18207774

申请日：2023-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunghee CHUNG ,  Hyeongjin KIM ,  Joongshik SHIN ,  Jeehoon HAN

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: A semiconductor device includes a source structure including a plate layer and first and second horizontal conductive layers stacked in order on the plate layer, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the source structure, a channel structure penetrating through the gate electrodes, extending in the first direction, and including a channel layer in contact with the first horizontal conductive layer, and a separation region penetrating through the gate electrodes and extending in the first direction and in a second direction perpendicular to the first direction, wherein the first horizontal conductive layer extends horizontally below the separation region and has a seam overlapping the separation region in the first direction.

公开(公告)号：US20240381641A1

公开(公告)日：2024-11-14

申请号：US18435342

申请日：2024-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungeun PARK ,  Solmi KWAK ,  Jinhyuk KIM ,  Hyeongjin KIM ,  Jeongyong SUNG ,  Minsoo SHIN ,  Seungjun SHIN ,  Joongshik SHIN ,  Sunghee CHUNG ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/40 ,  H10B43/40

Abstract: A vertical memory device may include a common source plate on a substrate including a first region and a second region; gate pattern structures on the common source plate and extending from the first region to the second region, wherein the gate pattern structures include gate patterns and first insulation layers, and wherein the adjacent gate pattern structures are spaced apart from each other; first separation patterns filling first openings between the adjacent gate pattern structures on the first region; second separation patterns filling second openings between the adjacent gate pattern structures on the second region, wherein at least one of the second separation patterns is connected to at least one of the first separation patterns, and wherein the second separation pattern has a shape different from a shape of the first separation pattern; and channel structures passing through the gate pattern structures on the first region.