公开(公告)号：US20230153181A1

公开(公告)日：2023-05-18

申请号：US17896788

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Hyun YANG ,  Sungju RYU ,  Ho Young KIM

IPC: G06F9/54 ,  G06F9/52 ,  G06N5/04

CPC classification number: G06F9/543 ,  G06F9/52 ,  G06N5/04

Abstract: Disclosed are electronic devices with predetermined compression schemes for parallel computing and methods thereof. An example electronic device includes cores of one or more processors, one or more memories storing instructions configured to, when executed by the cores, configure the cores to perform operations of an application executed on the electronic device, the operations including communication phases that communicate data between the cores, wherein the application includes, prior to execution of the application on the electronic device, predetermined information associating the communication phases with respective compression schemes, and apply the compression schemes corresponding to the communication phases according to the predetermined information to compress the data of the communication phases that is exchanged between the cores when executing the application.

公开(公告)号：US20240220786A1

公开(公告)日：2024-07-04

申请号：US18604268

申请日：2024-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungju RYU ,  Hyungjun KIM ,  Jae-Joon KIM

IPC: G06N3/063 ,  G06F7/485 ,  G06F7/523

CPC classification number: G06N3/063 ,  G06F7/485 ,  G06F7/523

Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.

公开(公告)号：US20230131035A1

公开(公告)日：2023-04-27

申请号：US18085939

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungju RYU ,  Hyungjun KIM ,  Jae-Joon KIM

IPC: G06N3/063 ,  G06F7/485 ,  G06F7/523

Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.