公开(公告)号：US20140164837A1

公开(公告)日：2014-06-12

申请号：US14070595

申请日：2013-11-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Se Hyun YANG

IPC: G06F11/277

CPC classification number: G06F11/277 ,  G06F11/267

Abstract: A multi-core processor includes a plurality of cores, each core configured to output an scan output pattern in response to an input of an scan input pattern, a multiplexing circuit configured to be responsive to a selection signal to output one of the scan output patterns output by the plurality of cores, and a comparison circuit configured to compare the scan output patterns with one another in units of bits, and to generate a plurality of comparison signals corresponding to comparison results.

Abstract translation: 多核处理器包括多个核心，每个核心配置成响应于扫描输入模式的输入而输出扫描输出模式;多路复用电路，被配置为响应于选择信号输出扫描输出模式之一 以及比较电路，被配置为将扫描输出模式以比特为单位进行比较，并且生成与比较结果对应的多个比较信号。

公开(公告)号：US20240160691A1

公开(公告)日：2024-05-16

申请号：US18316611

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  UIF (University Industry Foundation), Yonsei University

Inventor： Ho Young KIM ,  Min Sik KIM ,  Won Woo RO ,  Se Hyun YANG

IPC: G06F17/16 ,  G06F16/22

CPC classification number: G06F17/16 ,  G06F16/2237

Abstract: A method of operating a network switch for collective communication includes: receiving, via a network from external electronic devices, a first and second matrix each formatted according to a sparse matrix storage format; and generating a third matrix formatted according to the sparse matrix storage format, wherein the third matrix is generated by combining the first and second matrix according to the sparse matrix storage format, wherein, according to the sparse matrix storage format the first matrix includes first matrix positions of respective first element values and the second matrix includes second matrix positions of respective second element values, and wherein the combining includes comparing the first matrix positions with the second matrix positions.

公开(公告)号：US20230385025A1

公开(公告)日：2023-11-30

申请号：US18187971

申请日：2023-03-22

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Ho Young KIM ,  Won Woo RO ,  Se Hyun YANG ,  Dong Ho HA

IPC: G06F7/544

CPC classification number: G06F7/5443

Abstract: A processing device including a first buffer storing calculation rules, a calculator including a plurality of multipliers and an adder, the multipliers configured to perform multiplication repeatedly, a second buffer storing operands, the second buffer being configured to enqueue the operands based on the calculation rules into a queue, and a counter indicating a respective number indicating a number of times a multiplication is to be performed by each of the plurality of multipliers, each multiplier of the plurality of multipliers being configured to provide a non-final multiplication result to a first path to an input of the corresponding multiplier responsive to a corresponding number of multiplications performed by the multiplier being less than the respective number, and provide a final multiplication result to a second path to the adder responsive to the corresponding number of multiplications performed by the multiplier being equal to the respective number.

公开(公告)号：US20230369171A1

公开(公告)日：2023-11-16

申请号：US18358386

申请日：2023-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Jun HONG ,  Wonyong LEE ,  Alan GARA ,  Se Hyun YANG ,  Wooseok CHANG

IPC: H01L23/48 ,  H01L23/498 ,  G06F13/40 ,  H01L25/16 ,  H01L23/00

CPC classification number: H01L23/481 ,  H10B80/00 ,  H01L23/49838 ,  H01L23/49833 ,  G06F13/4022 ,  H01L25/16 ,  H01L23/49816 ,  H01L24/16 ,  H01L2924/1511 ,  H01L2924/1431 ,  H01L2224/16238 ,  H01L2224/16148 ,  H01L2924/14335 ,  H01L2224/16227 ,  H01L2924/1436 ,  H01L2924/1432

Abstract: A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.

公开(公告)号：US20230253294A1

公开(公告)日：2023-08-10

申请号：US18101565

申请日：2023-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonyong LEE ,  Alan GARA ,  Se Hyun YANG ,  Young Jun HONG ,  Wooseok CHANG

IPC: H01L23/48 ,  G06F13/40 ,  H01L25/16 ,  H10B80/00 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/481 ,  G06F13/4022 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/16 ,  H10B80/00 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1511 ,  H01L2924/14335

Abstract: A computing device includes: a processor; a memory stack in which memories connected to the processor are stacked; and a substrate disposed under the processor, wherein a network bandwidth between the processor and the substrate is five or less times a memory bandwidth between the processor and the memory stack.

公开(公告)号：US20230153181A1

公开(公告)日：2023-05-18

申请号：US17896788

申请日：2022-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Hyun YANG ,  Sungju RYU ,  Ho Young KIM

IPC: G06F9/54 ,  G06F9/52 ,  G06N5/04

CPC classification number: G06F9/543 ,  G06F9/52 ,  G06N5/04

Abstract: Disclosed are electronic devices with predetermined compression schemes for parallel computing and methods thereof. An example electronic device includes cores of one or more processors, one or more memories storing instructions configured to, when executed by the cores, configure the cores to perform operations of an application executed on the electronic device, the operations including communication phases that communicate data between the cores, wherein the application includes, prior to execution of the application on the electronic device, predetermined information associating the communication phases with respective compression schemes, and apply the compression schemes corresponding to the communication phases according to the predetermined information to compress the data of the communication phases that is exchanged between the cores when executing the application.