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公开(公告)号：US20230281436A1
公开(公告)日：2023-09-07
申请号：US18197093
申请日：2023-05-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Joon KIM , Jinseok KIM , Taesu KIM
Abstract: A method for processing data based on a neural network including a first layer including axons and a second layer including neurons, includes receiving synaptic weights between the first layer and the second layer; generating presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, from the synaptic weights; and storing the presynaptic weights and the postsynaptic weights in a synapse memory.
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公开(公告)号：US20230131035A1
公开(公告)日：2023-04-27
申请号：US18085939
申请日：2022-12-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungju RYU , Hyungjun KIM , Jae-Joon KIM
Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.
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公开(公告)号：US20250014638A1
公开(公告)日：2025-01-09
申请号：US18891682
申请日：2024-09-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinseok KIM , Yulhwa KIM , Jae-Joon KIM , Hyungjun KIM
IPC: G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US20230153594A1
公开(公告)日：2023-05-18
申请号：US18094351
申请日：2023-01-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Joon KIM , Hyungjun KIM , Yulhwa KIM
CPC classification number: G06N3/063 , G11C11/54 , G06N3/04 , G11C13/0069 , G11C13/004
Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.
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Patent Agency Ranking
公开(公告)号：US20230118943A1
公开(公告)日：2023-04-20
申请号：US18081837
申请日：2022-12-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jae-Joon KIM , Jinseok KIM , Taesu KIM
Abstract: A neuromorphic system includes an address translation device that translates an address corresponding to each of synaptic weights between presynaptic neurons and postsynaptic neurons to generate a translation address, and a plurality of synapse memories that store the synaptic weights based on the translation address. The translation address is generated such that at least two of synaptic weights corresponding to each of the postsynaptic neurons are stored in different synapse memories of the plurality of synapse memories and such that at least two of synaptic weights corresponding to each of the presynaptic neurons are stored in different synapse memories.
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公开(公告)号：US20210209190A1
公开(公告)日：2021-07-08
申请号：US17137803
申请日：2020-12-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaeha KUNG , Jae-Joon KIM , Junki PARK
Abstract: A matrix data processing method performed by a computing device which performs a matrix multiplication operation includes, with respect to each of one or more elements included in a matrix, when a value of each element satisfies a designated condition, determining the element to be a don't-care element and determining an output value of the don't-care element, generating a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix, and equally dividing the bitstream into pieces of a designated number, and generating a Huffman code corresponding to each of a plurality of lower bitstreams that are generated as a result of the equal division.
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公开(公告)号：US20240220786A1
公开(公告)日：2024-07-04
申请号：US18604268
申请日：2024-03-13
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sungju RYU , Hyungjun KIM , Jae-Joon KIM
Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature 5 bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number 10 of digits of the addition result depending on a shift value to generate a shifted addition result and an accumulator generating output feature data based on the shifted addition result.
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公开(公告)号：US20230260568A1
公开(公告)日：2023-08-17
申请号：US18303309
申请日：2023-04-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinseok KIM , Yulhwa KIM , Jae-Joon KIM , Hyungjun KIM
IPC: G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
CPC classification number: G11C11/412 , G06N3/08 , G11C11/418 , G11C11/419
Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.
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公开(公告)号：US20200184315A1
公开(公告)日：2020-06-11
申请号：US16561378
申请日：2019-09-05
Inventor： Sungho KIM , Yulhwa KIM , Hyungjun KIM , Jae-Joon KIM , Jinseok KIM
Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.
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